mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 417

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

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18.9.2 Multiple External Bus Device Arbitration Protocol
Three-wire mode lets the MCF5307 share the external bus with multiple external devices.
This mode requires an external arbiter to assign priorities to each potential master and to
determine which device accesses the external bus. The arbiter uses the MCF5307 bus
arbitration signals, BR, BD, and BG, to control use of the external bus by the MCF5307.
The MCF5307 requests the bus from the external bus arbiter by asserting BR when the core
requests an access. It continues to assert BR until after the transfer starts. It can negate BR
at any time regardless of the BG status. If the MCF5307 is granted the bus when an internal
bus request is generated, it asserts BD and the access begins immediately. The MCF5307
always drives BR and BD, which cannot be directly wire-ORed with other devices.
The external arbiter asserts BG to grant the bus to MCF5307, which can begin a bus cycle
after the next rising edge of BCLKO. If BG is negated during a bus cycle, the MCF5307
releases the bus when the cycle completes. To guarantee that the bus is released, BG must
be negated before the rising edge of the BCLKO in which the last TA is asserted. Note that
the MCF5307 treats any series of burst or a burst-inhibited transfers as a single bus cycle
and does not release the bus until the last transfer of the series completes.
When the MCF5307 is granted the bus after it asserts BR, one of two things can occur. If
the MCF5307 has an internal bus request pending, it asserts BD, indicating explicit bus
mastership, and begins the pending bus cycle by asserting TS. The MCF5307 continues to
assert BD until the external bus arbiter negates BG, after which BD is negated at the
completion of the bus cycle. As long as BG is asserted, BD remains asserted to indicate that
the MCF5307 is bus master, and the MCF5307 continuously drives the address bus,
attributes, and control signals.
If no internal request is pending, the MCF5307 takes implicit bus mastership. It does not
drive the bus and does not assert BD if the bus has an implicit master. If an internal bus
request is generated, the MCF5307 assumes explicit bus mastership and immediately
begins an access and asserts BD. Figure 18-30 shows implicit and explicit bus mastership
due to generation of an internal bus request.
Both normal terminations and terminations due to bus errors generate an end of cycle. Bus cycles resulting from
a burst-inhibited transfer are considered part of that original transfer.
A means asserted.
N means negated.
EM means external master.
(Three-Wire Mode)
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 18. Bus Operation
Go to: www.freescale.com
General Operation of External Master Transfers
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