s29ns01gr Meet Spansion Inc., s29ns01gr Datasheet - Page 14

• Manufacturer Part Number: s29ns01gr
• Description: S29ns01gr 1gb 64 M X 16 Bit , 1.8 V Burst Simultaneous Read/write, Multiplexed Mirrorbit Flash Memory
• Manufacturer: Meet Spansion Inc.

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Product Overview
The S29NS-R family consists of 128 Mbit to 1 Gbit, 1.8-V only, simultaneous read/write, burst-mode, Flash
devices. These devices have a 16 bit (word) wide data bus. All read accesses provide 16 bits of data on each
bus transfer cycle. All writes take 16 bits of data from each bus transfer cycle.
The Flash memory array is divided into banks as shown in the above table. A bank is the address range
within which one program, or erase operation may be in progress at the same time as one read operation is in
progress in any other bank of the memory. This multiple bank structure enables Simultaneous Read and
Write (SRW) so that code may be executed or data read from one bank while a group of data is programmed,
or erased as a background task in one other bank.
Each bank is divided into sectors. A sector is the minimum address range of data which can be erased to an
all Ones state. There may be four 32-KByte sectors located at the top of the memory array depending on the
device model purchased. These are called boot sectors because they are often used for holding boot code or
parameters that need to be protected or erased separately from other data in the Flash array. All other
sectors are a uniform size of 128-KBytes.
Programming is done via a 64 Byte write buffer. It is possible to program from one to 32 words (64 bytes) in
each programming operation.
The S29NS family is capable of continuous, synchronous (burst) read or linear read (8- or 16-word aligned
group) with wrap around. A wrapped burst begins at the initial location and continues to the end of an 8, or 16-
word aligned group then “wraps-around” to continue at the beginning of the 8, or 16-word aligned group. The
burst completes with the last word before the initial location. Word wrap around burst is generally used for
processor cache line fill.
S29NS01G-R
S29NS128-R
S29NS256-R
S29NS512-R
Device
D a t a
S29NS-R MirrorBit
S h e e t
Mbits
1024
128
256
512
( A d v a n c e
®
Flash Family
Mbytes
128
16
32
64
Mwords
I n f o r m a t i o n )
16
32
64
8
Banks
16
16
16
16
S29NS-R_00_03 May 9, 2008
Mbytes / Bank
1
2
4
8