s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 180

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Serial Peirpheral Interface (SPI)
17.12.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
17.12.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
17.5 Transmission Formats
high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
throughout the transmission for the CPHA = 1 format. See
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. (See
Register).
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the data register. (See
180
X = don’t care
SPE
0
1
1
1
MASTER SS
SPMSTR
MISO/MOSI
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if a transmission already has begun.
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
X
0
1
1
MODFEN
Since it is used to indicate the start of a transmission, the SS must be toggled
X
X
0
1
Table
BYTE 1
MC68HC908AZ32A Data Sheet, Rev. 2
Figure 17-11. CPHA/SS Timing
Master without MODF
Table 17-4. SPI Configuration
SPI Configuration
Master with MODF
17-4.)
Not Enabled
Slave
NOTE
BYTE 2
Figure
General-Purpose I/O; SS Ignored by SPI
General-Purpose I/O; SS Ignored by SPI
17.6.2 Mode Fault
17-11.
17.13.2 SPI Status and Control
State of SS Logic
Input-Only to SPI
Input-Only to SPI
BYTE 3
Error). For the state of
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