s908ab32ag0cfue Freescale Semiconductor, Inc, s908ab32ag0cfue Datasheet - Page 201

• Manufacturer Part Number: s908ab32ag0cfue
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

12.5.3 Output Compare
12.5.3.1 Unbuffered Output Compare
MC68HC908AB32
Freescale Semiconductor
—
Rev. 1.1
With the output compare function, the TIMB can generate a periodic
pulse with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIMB can set, clear, or toggle the channel pin. Output compares can
generate TIMB CPU interrupt requests.
Any output compare channel can generate unbuffered output compare
pulses as described in
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIMB overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMB may
pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
•
•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
When changing to a larger output compare value, enable
channel x TIMB overflow interrupts and write the new value in the
TIMB overflow interrupt routine. The TIMB overflow interrupt
occurs at the end of the current counter overflow period. Writing a
larger value in an output compare interrupt routine (at the end of
the current pulse) could cause two output compares to occur in the
same counter overflow period.
Timer Interface Module B (TIMB)
12.5.3 Output
Compare. The pulses are
Timer Interface Module B (TIMB)
Technical Data
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