ad7883br Analog Devices, Inc., ad7883br Datasheet - Page 3

• Manufacturer Part Number: ad7883br
• Description: Lc2mos 12-bit, 3.3 V Sampling Adc
• Manufacturer: Analog Devices, Inc.

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TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
NOTES
1
2
3
DB0 – DB11
Timing specifications in bold print are 100% production tested. All other times are sample tested at +25 C to ensure compliance. All input signals are specified with
t
t
1
2
3
4
5
6
7
8
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
lated back to remove the effects of charging the 50 pF capacitor. This means that the time, t
the part and as such is independent of external bus loading capacitances.
7
8
2
3
CONVST
is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.
is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapo-
BUSY
CS
RD
t
1
Figure 1. Timing Diagram
t
2
Limit at +25 C
(All Versions)
50
200
0
0
0
110
100
5
90
TRACK/HOLD
GOES INTO HOLD
THREE-STATE
t
CONVERT
1
(V
t
3
SS
Limit at T
(All Versions)
60
200
0
0
0
150
140
5
90
= +3 V to +3.6 V, V
t
4
t
7
t
6
VALID
DATA
MIN
t
t
5
8
, T
MAX
REF
–3–
= V
CS
1
1
0
0
Model
AD7883BN
AD7883BR
*N = Plastic DIP; R = SOIC (Small Outline Integrated Circuit).
DD
Figure 2. Load Circuit for Access and Relinquish Time
, AGND = DGND = 0 V)
8
, quoted in the timing characteristics is the true bus relinquish time of
Units
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
CONVT
1
j
1
1
OUTPUT
PIN
TO
Temperature Range
–40 C to +85 C
–40 C to +85 C
50pF
ORDERING GUIDE
Table I. Truth Table
RD
X
1
0
1
Conditions/Comments
CONVST Pulse Width
CONVST to BUSY Falling Edge
BUSY to CS Setup Time
CS to RD Setup Time
CS to RD Hold Time
RD Pulse Width
Data Access Time after RD
Bus Relinquish Time after RD
0.8mA
200 A
Function
Not Selected
Start Conversion g
Enable ADC Data
Data Bus Three Stated
Package Option*
N-24
R-24
AD7883
+1.6V