ad7883br Analog Devices, Inc., ad7883br Datasheet - Page 6

• Manufacturer Part Number: ad7883br
• Description: Lc2mos 12-bit, 3.3 V Sampling Adc
• Manufacturer: Analog Devices, Inc.

AD7883
The AD7883 has one unipolar input range, 0 V to V
4 shows the analog input for this range. The designed code
transitions occur midway between successive integer LSB val-
ues (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The
output code is straight binary with 1 LSB = FS/4096 = 3.3 V/
4096 = 0.8 mV when V
transfer characteristic for the unipolar range is shown in Figure 6.
Figure 5 shows the AD7883’s V
figuration. Once again the designed code transitions occur mid-
way between successive integer LSB values. The output code is
straight binary with 1 LSB = FS/4096 = 6.6 V/4096 = 1.6 mV.
The ideal bipolar input/output transfer characteristic is shown
in Figure 7.
000...010
111...110
111...100
000...000
OUTPUT
111...111
111...101
000...011
000...001
111...111
111...110
100...101
100...000
000...000
011...110
011...111
000...001
CODE
Figure 6. Unipolar Transfer Characteristics
Figure 7. Bipolar Transfer Characteristic
0V
OUTPUT
CODE
1LSB
–FS
2
REF
V
IN
= 3.3 V. The ideal input/output
INPUT VOLTAGE
–1LSB
V
IN
INPUT VOLTAGE
REF
0V
1LSB =
bipolar analog input con-
+1LSB
4096
1LSB =
FS
FS = 10V
+
FS – 1LSB
4096
+FS
FS
2
REF
– 1LSB
. Figure
–6–
CLOCK INPUT
The AD7883 is specified to operate with a 2 MHz clock con-
nected to the CLKIN input pin. This pin may be driven directly
by CMOS buffers. The mark/space ratio on the clock can vary
from 40/60 to 60/40. As the clock frequency is slowed down, it
can result in slightly degraded accuracy performance. This is
due to leakage effects on the hold capacitor in the internal
track-and-hold amplifier. Figure 8 is a typical plot of accuracy
versus clock frequency for the ADC.
TRACK/HOLD AMPLIFIER
The charge balanced comparator used in the AD7883 for the
A/D conversion provides the user with an inherent track/hold
function. The track/hold amplifier acquires an input signal to
12-bit accuracy in less than 5 s. The overall throughput time is
equal to the conversion time plus the track/hold amplifier acqui-
sition time. For a 2 MHz input clock, the throughput time is
20 s.
The operation of the track/hold amplifier is essentially transpar-
ent to the user. The track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion, i.e., on the ris-
ing edge of CONVST as shown in Figure 1.
OFFSET AND FULL-SCALE ADJUSTMENT
In most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Some applications will require that the input
signal range match the maximum possible dynamic range of the
ADC. In such applications, offset and full-scale error will have
to be adjusted to zero.
The following sections describe suggested offset and full-scale
adjustment techniques which rely on adjusting the inherent off-
set of the op amp driving the input to the ADC as well as tweak-
ing an additional external potentiometer as shown in Figure 9.
Figure 8. Normalized Linearity Error vs. Clock Frequency
2.5
2.0
1.5
1.0
0.0
0.5
1.0
CLOCK FREQUENCY – MHz
2.0
3.0
REV. 0