ad7450ar-reel7 Analog Devices, Inc., ad7450ar-reel7 Datasheet - Page 4

• Manufacturer Part Number: ad7450ar-reel7
• Description: Differential Input, 1 Msps 12-bit Adc In
  soic-8 And So-8
• Manufacturer: Analog Devices, Inc.

AD7450
TIMING SPECIFICATIONS
f
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
See Figure 1 and the Serial Interface section.
Common-mode voltage.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
t
See Power-Up Time section.
SCLK
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
0.4 V or 2.0 V for V
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
8
5
5
6
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
SDATA
SCLK
= 18 MHz, f
4
CS
7
S
3 V
50
15
16
1.07
25
10
10
20
40
0.4 t
0.4 t
10
10
35
1
= 1 MSPS, V
DD
t
Limit at T
2
0
= 3 V.
SCLK
SCLK
t
4 LEADING ZEROS
1
SCLK
t
3
0
REF
MIN
2
50
18
16
0.88
25
10
10
20
40
0.4 t
0.4 t
10
10
35
1
= 2.5 V; V
5 V
, T
0
SCLK
SCLK
MAX
t
SCLK
1, 2
3
CM
3
(V
= V
0
Figure 1. Serial Interface Timing Diagram
DD
Unit
kHz min
MHz max
µs max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
REF
t
= 2.7 V to 3.3 V, f
4
4
; T
DB11
A
t
= T
5
MIN
t
CONVERT
5
to T
Description
t
SCLK = 15 MHz, 18 MHz
Minimum Quiet Time between the End of a Serial Read and the Next
Falling Edge of CS
Minimum CS Pulsewidth
CS Falling Edge to SCLK Falling Edge Setup Time
Delay from CS Falling Edge until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Edge to Data Valid Hold Time
SCLK Falling Edge to SDATA Three-State Enabled
SCLK Falling Edge to SDATA Three-State Enabled
Power-Up Time from Full Power-Down
DB10
t
7
SCLK
MAX
SCLK
, unless otherwise noted.)
= 1/f
–4–
= 15 MHz, f
SCLK
13
S
DB2
= 833 kSPS, V
8
, quoted in the timing characteristics is the true bus relinquish
14
t
6
DB1
DD
REF
15
) and timed from a voltage level of 1.6 V.
= 1.25 V; V
t
8
DB0
DD
= 5 V, and the time for an output to cross
16
THREE-STATE
DD
= 4.75 V to 5.25 V,
t
QUIET
t
1
REV. 0