ad7650astrl Analog Devices, Inc., ad7650astrl Datasheet - Page 16

• Manufacturer Part Number: ad7650astrl
• Description: 16-bit, 570 Ksps Low Cost Cmos Adc
• Manufacturer: Analog Devices, Inc.

AD7650
CNVST IN
SCLK IN
CS IN
RDC/SDIN
(UPSTREAM)
AD7650
BUSY
#2
SDOUT
CNVST
SCLK
CS
SDOUT
CNVST
SDOUT
BUSY
SCLK
BUSY
SCLK
SDIN
CS
CS
t
16
t
t
31
16
t
RDC/SDIN
3
(DOWNSTREAM)
t
t
AD7650
33
31
BUSY
X
X
#1
t
t
36
1
36
1
t
SDOUT
CNVST
t
35
D15
35
SCLK
t
D15
X15
37
t
37
CS
t
34
2
2
EXT/INT = 1
D14
D14
t
X14
EXT/INT = 1
32
BUSY OUT
t
DATA OUT
32
3
3
D13
X13
D13
External Clock Data Read During Conversion
Figure 16 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are both low, the
result of the previous conversion can be read. The data is shifted
out, MSB first, with 16 clock pulses and is valid on both rising
and falling edge of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no “daisy chain”
feature in this mode and RDC/SDIN input should always be tied
either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of, at least 18 MHz, when impulse mode is
used, 25 MHz when normal mode is used or 40 MHz when
warp mode is used, is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue to
read the last bits even after a new conversion has been initiated.
That allows the use of a slower clock speed like 14 MHz in impulse
mode, 18 MHz in normal mode and 25 MHz in warp mode.
INVSCLK = 0
INVSCLK = 0
14
14
15
15
D1
X1
D1
16
16
RD = 0
RD = 0
D0
X0
D0
17
X15
Y15
18
X14
Y14