mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 49

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

WRITEs
Figure 26:
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
WRITE Burst
Notes:
WRITE bursts are initiated with a WRITE command, as shown in Figure 10 on page 26.
The starting column and bank addresses are provided with the WRITE command and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the
WRITE command. Subsequent data elements are registered on each successive positive
clock edge. Upon completion of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and any additional input data will be
ignored (see Figure 26 on page 49). A continuous page burst continues until terminated;
at the end of the page, it wraps to column 0 and continues.
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 27 on page 50. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. Mobile SDRAMs use a pipelined
architecture and therefore do not require the 2n rule associated with a prefetch architec-
ture. A WRITE command can be initiated on any clock cycle following a previous WRITE
command. Full-speed random write accesses within a page can be performed to the
same bank, as shown in Figure 28 on page 51, or each subsequent WRITE may be
performed to a different bank.
1. BL = 2. DQM is LOW.
Command
Address
CLK
DQ
WRITE
Bank,
Col n
T0
D
Transitioning Data
n
IN
NOP
n + 1
T1
D
IN
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
49
NOP
T2
Don’t Care
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
©2008 Micron Technology, Inc. All rights reserved.
Timing Diagrams
Preliminary