mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 56

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Concurrent Auto Precharge
READ with Auto Precharge
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst,
except in the continuous page burst mode, where auto precharge does not apply. In the
specific case of write burst mode set to single location access with burst length set to
continuous, the burst length setting is the overriding setting and auto precharge does
not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each
individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (
issued at the earliest possible time, as described for each burst type in the Burst Type
section on page 36.
This device supports
a single WRITE with auto-precharge, issued at
delayed until
Initiating an access command (READ or WRITE) to a second bank while an access
command with auto precharge enabled on a first bank is executing is not supported by
SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs
support concurrent auto precharge. Four cases where concurrent auto precharge occurs
are defined below; two are for READ with auto precharge, two are for WRITE with auto
precharge.
rupt a READ on bank n, CL later. The precharge to bank n begins when the READ to
bank m is registered (see Figure 35).
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n begins
when the WRITE to bank m is registered (see Figure 36 on page 57).
t
RP) is completed. This is determined as if an explicit PRECHARGE command was
t
RAS min has been satisfied.
t
RAS lock-out. In the case of a single READ with auto-precharge, or
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD min, the internal precharge will be
©2008 Micron Technology, Inc. All rights reserved.
Timing Diagrams
Preliminary