mt46h32m32lfjg-6it Micron Semiconductor Products, mt46h32m32lfjg-6it Datasheet - Page 7

• Manufacturer Part Number: mt46h32m32lfjg-6it
• Description: Nand Flash And Mobile Lpdram 168-ball Package-on-package Pop Mcp Combination Memory Ti Omap?
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09
Note:
Table 2: x8, x16 NAND Ball Descriptions
1. Balls marked RFU may or may not be connected internally. These balls should not be
I/O[15:0] (x16)
I/O[7:0] (x8)
CE0#, CE1#
used. Contact factory for details.
Symbol
LOCK
WE#
WP#
R/B#
ALE
RE#
CLE
Vcc
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Output Ready/busy: Open-drain, active-LOW output that indicates
output
Supply
Input/
Type
Input
Input
Input
Input
Input
Input
Input
Address latch enable: When ALE is HIGH, addresses can be
transferred to the on-chip address register.
Chip enable: Gates transfers between the host system and
the NAND device.
CE1# is used when a second CE# is required and is RFU in all
other configurations.
Command latch enable: When CLE is HIGH, commands can be
transferred to the on-chip command register.
When LOCK is HIGH during power-up, the BLOCK LOCK func-
tion is enabled. To disable BLOCK LOCK, connect LOCK to Vss
during power-up, or leave it unconnected (internal pull-down).
Read enable: Gates information from the NAND device to the
host system.
Write enable: Gates information from the host system to the
NAND device.
Write protect: Driving WP# LOW blocks ERASE and
PROGRAM operations.
Data inputs/outputs: The bidirectional I/Os transfer address,
data, and instruction information. Data is output only during
READ operations; at other times the I/Os are inputs.
I/O[15:8] are RFU
when an internal operation is in progress.
Vcc: NAND power supply.
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
1
for NAND x8 devices.
Description
©2007 Micron Technology, Inc. All rights reserved.