mt4lc4m16r6 Micron Semiconductor Products, mt4lc4m16r6 Datasheet
mt4lc4m16r6
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mt4lc4m16r6 Summary of contents
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... Self Refresh • Operating Temperature Range Commercial (0°C to +70°C) Extended (-40°C to +85°C) NOTE: 1. The “#” symbol indicates signal is active LOW. *Contact factory for availability. **Available only on MT4LC4M16R6 standard refresh device. Part Number Example: MT4LC4M16R6TG-5 KEY TIMING PARAMETERS ...
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... REFRESH CONTROLLER A0- A12 REFRESH COUNTER ROW- ADDRESS 13 BUFFERS (13) NO. 1 CLOCK RAS# GENERATOR 4 Meg x 16 EDO DRAM D29_2.p65 – Rev. 5/00 FUNCTIONAL BLOCK DIAGRAM MT4LC4M16R6 (12 row addresses) CAS# DATA-IN BUFFER 4,096 FUNCTIONAL BLOCK DIAGRAM MT4LC4M16N3 (13 row addresses) CAS# DATA-IN BUFFER 8192 2 ...
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... The device is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns on the MT4LC4M16R6 or 8,192 rows by 512 columns on the MT4LC4M16N3. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 row-address bits (A0-A11) and 10 ...
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DRAM ACCESS (continued) the upper byte (DQ8-DQ15). General byte and word access timing is shown in Figures 1 and 2. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE ...
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V IH RAS CAS ADDR ROW COLUMN ( IOH DQ OPEN V IOL RAS CAS ...
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... CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC4M16N3 internally refreshes two rows for each CBR cycle, whereas the MT4LC4M16R6 refreshes one row for every CBR cycle. For either device, executing 4,096 CBR cycles will refresh the entire de- vice ...
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... This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Available only on MT4LC4M16R6 standard refresh device. + 0.3V); £ 0.3V); CC ...
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Icc OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes +3.3V ±0.3V) CC PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS STANDBY CURRENT: CMOS (RAS# = CAS# ³ 0.2V; DQs may ...
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CAPACITANCE (Note: 2) PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 CHARACTERISTICS PARAMETER Access time from column address Column-address setup ...
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AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 CHARACTERISTICS PARAMETER EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row address hold time RAS# ...
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... WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 22. RAS#-ONLY REFRESH requires that all 8,192 rows = 2V. of the MT4LC4M16N3 or all 4,096 rows of the OH MT4LC4M16R6 be refreshed at least once every 64ms. 23. CBR REFRESH for either device requires that at t CP. least 4,096 cycles be completed every 64ms. ...
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NOTES (continued) 28. Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#. 29. Each CASx# must meet minimum pulse width. 30. The last CASx# edge to transition HIGH. 31. Last falling CASx# edge ...
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V IH RAS CRP V CAS ASR V IH ROW ADDR WE OE TIMING PARAMETERS -5 SYMBOL MIN ...
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V IH RAS CRP CAS ASR V IH ADDR ROW IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN ...
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WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS ASR V IH ADDR ROW WE IOH DQ V IOL ...
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V IH RAS CSH t CRP V CAS RAD t ASR t RAH V IH ADDR V ROW OPEN OE# ...
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EDO-PAGE-MODE EARLY WRITE CYCLE V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR ROW WCS ...
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WRITE and READ-MODIFY-WRITE cycles RAS CRP CASL#/CASH RAD t ASR t RAH V IH ADDR V ROW IL WE IOH DQ V ...
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EDO-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP t RCD V IH CAS RAD t ASR t RAH V IH ADDR ROW WE IOH DQ OPEN ...
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V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR WE OE TIMING PARAMETERS -5 SYMBOL MIN MAX ...
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V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR RAS RPC CASL#/CASH ...
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V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR ROW IOH DQx V IOL TIMING PARAMETERS -5 SYMBOL MIN MAX MIN ...
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RAS RPC CSR V IH CASL CASH WRP TIMING PARAMETERS -5 SYMBOL MIN MAX MIN t CHD ...
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TYP PIN #1 ID NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. Federal ...