mt47h256m8thn-3 Micron Semiconductor Products, mt47h256m8thn-3 Datasheet - Page 4

• Manufacturer Part Number: mt47h256m8thn-3
• Description: 2gb X4, X8 Twindie Ddr2 Sdram Functionality
• Manufacturer: Micron Semiconductor Products

Table 3:
PDF: 09005aef8266acfe/Source: 09005aef8266ac6e
MT47H512M4_32M_16M_twindie.fm - Rev. B 1/08 EN
Ball Numbers
A1, E9, H9, L1
H8, H3, H7,
C8, C2, D7,
C8, C2, D7,
J7, K2, K8,
D9, B1, B9
J2, J8, J3,
G2, G3,
D3, D1,
K3, H2,
K7, L2,
G8, G9
F7, G7,
A8, B7
A2, B3
F2, H1
E8, F8
F9, J9
G1
B3
D3
L8
F3
63-Ball FBGA Ball Descriptions – x4, x8
ODT0, ODT1
RAS#, CAS#,
CKE0, CKE1
A0, A1, A2,
A3, A4, A5,
A6, A7, A8,
DQS#, DQS
CS0#, CS1#
DQ0, DQ1,
DQ0, DQ1,
DQ3, DQ4,
DQ5, DQ6,
BA0, BA1,
A11, A12,
Symbol
A9, A10,
CK, CK#
RDQS#,
RDQS
DQ2,
DQ2,
WE#
DQ3
DQ7
A13
BA2
V
DM
DD
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA0–BA2) or all banks (A10
HIGH). The address inputs also provide the op-code during a LOAD MODE
command.
Bank address inputs: BA0–BA2 define the bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA2 define which
mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the
LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the negative
edge of CK#. Output data (DQ, DQS, and DQS#) are referenced to the crossings
of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW)
the internal circuitry and clocks on the DDR2 SDRAM.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH.
CS# provides for external rank selection on systems with multiple ranks. CS# is
considered part of the command code.
Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with the input data during a write
access. DM is sampled on both edges of DQS. Although DM balls are input-
only, the DM loading is designed to match that of the DQ and DQS balls.
On-die termination: ODT enables (registered HIGH) and disables (registered
LOW) termination resistance internal to the DDR2 SDRAM. When enabled,
ODT is only applied to each of the following balls: DQ0–DQ7, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Data input/output: Bidirectional data bus for the x4 configuration.
Data input/output: Bidirectional data bus for the x8 configuration.
Data strobe: Output with read data. Edge-aligned with read data. Input with
write data for source-synchronous operation. Center-aligned with write data.
DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
Redundant data strobe: For the x8 configuration only. RDQS is enabled/
disabled via the LOAD MODE command to the extended mode register (EMR).
When RDQS is enabled, RDQS is output with read data only and is ignored
during write data. When RDQS is disabled, B3 becomes data mask (see DM
ball). RDQS# is only used when both RDQS and the differential data strobe
mode are enabled.
Power supply: 1.8V ±0.1V.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
2Gb: x4, x8 TwinDie DDR2 SDRAM
©2006 Micron Technology, Inc. All rights reserved