hef40195b NXP Semiconductors, hef40195b Datasheet - Page 2

• Manufacturer Part Number: hef40195b
• Description: 4-bit Universal Shift Register
• Manufacturer: NXP Semiconductors

Philips Semiconductors
DESCRIPTION
The HEF40195B is a fully synchronous edge-triggered
4-bit shift register with a clock input (CP), four synchronous
parallel data inputs (P
inputs (J, K), a synchronous parallel enable input (PE),
buffered parallel outputs from all 4-bit positions (O
a buffered inverted output from the last bit position (O
and an overriding asynchronous master reset input (MR).
Each register stage is of a D-type master-slave flip-flop.
Operation is synchronous (except for MR) and is
edge-triggered on the LOW to HIGH transition of the CP
January 1995
4-bit universal shift register
Fig.2 Pinning diagram.
0
to P
3
), two synchronous serial data
Fig.1 Functional diagram.
0
to O
3
)
3
),
2
input. When PE is LOW, data are loaded into the register
from P
PE is HIGH, data are shifted into the first register position
from J and K and all the data in the register are shifted one
position to the right on the LOW to HIGH transition of CP.
D-type entry is obtained by interconnecting J and K.
When J is HIGH and K is LOW, the first stage is in the
toggle mode. When J is LOW and K is HIGH, the first stage
is in the hold mode.
A LOW on MR resets all four bit positions (O
O
conditions.
FAMILY DATA, I
See Family Specifications
HEF40195BP(N):
HEF40195BD(F):
HEF40195BT(D):
( ): Package Designator North America
3
= LOW, O
0
to P
3
3
on the LOW to HIGH transition of CP. When
= HIGH) independent of all other input
DD
LIMITS category MSI
16-lead DIL; plastic
16-lead DIL; ceramic (cerdip)
16-lead SO; plastic
(SOT38-1)
(SOT74)
(SOT109-1)
Product specification
HEF40195B
0
to
MSI