hef4517b NXP Semiconductors, hef4517b Datasheet - Page 2

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hef4517b

Manufacturer Part Number
hef4517b
Description
Dual 64-bit Static Shift Register
Manufacturer
NXP Semiconductors
Datasheet

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DESCRIPTION
The HEF4517B consists of two identical, independent
64-bit static shift registers. Each register has separate
clock (CP), data input (D), parallel
input-enable/output-enable (PE/EO) and four 3-state
outputs of the 16th, 32nd, 48th and 64th bit positions
(O
on the LOW to HIGH transition of the clock, regardless of
the state of PE/EO.
FAMILY DATA, I
See Family Specifications
January 1995
Dual 64-bit static shift register
16
to O
64
). Data at the D input is entered into the first bit
DD
LIMITS category LSI
Fig.1 Functional diagram.
2
When PE/EO is LOW the outputs are enabled and the
device is in the 64-bit serial mode.
When PE/EO is HIGH the outputs are disabled (high
impedance OFF-state), the 64-bit shift register is divided
into four 16-bit shift registers with D, O
data inputs of the 1st, 17th, 33rd, and 49th bit respectively.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Product specification
HEF4517B
16
, O
32
and O
LSI
48
as

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