adf4196 Analog Devices, Inc., adf4196 Datasheet
adf4196
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adf4196 Summary of contents
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... SET REFERENCE SW1 PHASE CP + CHARGE OUT+ PUMP – CP DETECTOR OUT– SW2 CMR DIFFERENTIAL AMPLIFIER AIN– – + AIN+ A OUT SW3 RF IN+ RF IN– INTEGER REG ADF4196 GND GND ©2011 Analog Devices, Inc. All rights reserved. ADF4196 www.analog.com ...
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... Phase Register (R2) Bit Latch Map .......................................... 17 Function Register (R3) Latch Map ........................................... 18 Charge Pump Register (R4) Latch Map .................................. 19 Power-Down Register (R5) Bit Map ........................................ 20 Mux Register (R6) Latch Map and Truth Table ..................... 21 Programming the ADF4196 .......................................................... 22 Worked Example ........................................................................ 22 Spur Mechanisms ....................................................................... 22 Power-Up Initialization ............................................................. 23 Changing the Frequency of the PLL and the Phase Lookup Table ...
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... − 1 nV/√ kHz offset V V µ 500 µ 500 µ ≤ ≤ 5 ≤ ≤ 5. µA ADF4196 GND GND ...
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... ADF4196 Parameter SW1, SW2, AND SW3 On Resistance SW1 and SW2 SW3 NOISE CHARACTERISTICS Output 900 MHz 2 1800 MHz 3 Phase Noise Normalized Phase Noise Floor ( SYNTH Normalized 1/f Noise ( 1_f Choose a prescaler value that ensures that the frequency on the RF input is less than the maximum allowable prescaler frequency (750 MHz). ...
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... Table 4. Thermal Resistance Package Type 32-Lead LFCSP (Paddle Soldered TRANSISTOR COUNT 0 This device includes 75,800 metal oxide semiconductors (MOS and 545 bipolar junction transistors (BJT). ESD CAUTION Rev Page ADF4196 θ Unit JA 27.3 °C/W ...
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... Ground Return Pin for V GND Ground Return Pin for V GND CMR 1 PIN OUT INDICATOR SW3 GND ADF4196 RF 5 IN– TOP VIEW RF 6 IN+ (Not to Scale NOTES 1. THE EXPOSED PADDLE MUST BE CONNECTED TO THE GROUND PLANE. Figure 3. Pin Configuration 3. Requires a 0.1 µ ...
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... I = 104 µA. SET CP 2 should be at the same voltage when the SW1/SW2 timeout counter is active. GND when the SW1/SW2 timeout counter is active. GND 3 also requires a 10 µF decoupling capacitor to the ground plane. P Rev Page Place a 0.1 µF P ADF4196 ...
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... ADF4196 TYPICAL PERFORMANCE CHARACTERISTICS FREQ. UNIT GHz KEYWORD R PARAM TYPE S IMPEDANCE 50 DATA FORMAT MA FREQ. MAGS11 ANGS11 FREQ. 0.5 0.8897 –16.6691 2.3 0.6 0.87693 –19.9279 2.4 0.7 0.85834 –23.561 2.5 0.8 0.85044 –26.9578 2.6 0.9 0.83494 –30.8201 2.7 1.0 0.81718 –34.9499 2.8 1.1 0.80229 –39.0436 2.9 1.2 0.78917 –42.3623 3 ...
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... V to 1.8 V with Sirenza 1843T VCO) to 1818 MHz (V TUNE 5. 3.3V CMR OUT TUNE AIN+) OUT OUT– 0 1780 1800 1820 1840 1860 1880 1900 FREQUENCY (MHz) Amplifier Power Supply Voltage ADF4196 AIN–) 1920 1940 ...
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... ADF4196 1000 100 7nV 20kHz 10k 100k FREQUENCY (Hz) Figure 16. Voltage Noise Density Measured at the Differential Amplifier Output 100 SW3 90 +85°C SW1, 80 SW2 +85°C +25°C 70 +25°C –40° –40°C 40 TUNING VOLTAGE RANGE DRAIN VOLTAGE (V) Figure 17 ...
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... The value of MOD is chosen to give the desired channel step IN with the available reference frequency. Then, program the INT and FRAC words for the desired RF output frequency. See the Worked Example section for more information. Rev Page ADF4196 AV DD 1.6V BIAS GENERATOR 500Ω ...
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... ADF4196 PFD AND CHARGE PUMP The PFD takes inputs from the R divider and N divider and produces up and down outputs with a pulse width difference that is proportional to the phase difference between the inputs. The charge pump outputs a net up or down current pulse of a width that is equal to this difference, to pump up or pump down the voltage that is integrated into the loop filter, which in turn increases or decreases the VCO output frequency ...
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... Control Bits C2 (DB1) C1 (DB0) Register Name 0 0 FRAC/INT 0 1 MOD Phase 1 1 Function 0 0 Charge pump 0 1 Power-down 1 0 Mux 1 1 Test mode ADF4196 DV DD MUX OUT D GND Register ...
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... ADF4196 REGISTER MAP 9-BIT RF INT VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DBB DBB DBB 4-BIT RF R COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 ...
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... DB6 DB5 DB4 DB3 FRACTIONAL VALUE (FRAC 4092 0 1 4093 1 0 4094 1 1 4095 0 ≤ FRAC < MOD INTEGER VALUE (INT 511 ADF4196 CONTROL BITS DB2 DB1 DB0 C3 (0) C2 (0) C1 (0) ...
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... Modulus For a given PFD reference frequency, the fractional denominator or modulus sets the channel step resolution at the RF output. All integer values from 13 to 4095 are allowed. See the Programming the ADF4196 selecting the value of MOD. Rev Page DB9 DB8 DB7 ...
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... Register R0 must be an integer multiple of MOD reference cycles. To keep the outputs of two ADF4196-based synthesizers phase coherent with each other (but not necessarily with the reference they have in common), the write to Register R0 on both chips must be performed during the same reference cycle ...
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... ADF4196 FUNCTION REGISTER (R3) LATCH MAP DB15 DB14 DB13 R3, the function register, needs to be programmed only during the initialization sequence (see Table 9). Control Bits Register R3 is selected with C3, C2, and C1 set CPO GND When the CPO GND bit is low, the charge pump outputs are internally pulled to ground ...
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... DELAY WITH 26MHz PFD ADF4196 Timeout Time (µs) with Counter Value PFD = 13 MHz I 28 8.6 CP SW3 35 10.8 SW1/SW2 35 10.8 ADF4196 CONTROL BITS DB2 DB1 DB0 C2 (0) C1 (0) 1 DELAY µs 0 0.15 0.30 0. 78.15 78.30 78.46 78.61 for correct , CP ...
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... R5, the power-down register, can be used to power down the PLL and differential amplifier sections. After power is initially applied, Register R5 must be programmed to clear the power-down bits. Then, before the ADF4196 comes out of power-down, the R2, R1, and R0 registers must be programmed. Control Bits Register R5 is selected with C3, C2, and C1 set ...
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... SERIAL DATA OUTPUT 1 1 LOGIC LOW DIVIDER/2 OUTPUT DIVIDER/2 OUTPUT 1 0 RESERVED 1 1 RESERVED 0 TIMEOUT SIGNAL SW1/SW2 TIMEOUT SIGNAL 1 0 SW3 TIMEOUT SIGNAL 1 1 RESERVED Modes . For example, if the I OUT pin. OUT pin. OUT ADF4196 timeout CP ...
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... The interval between spurs is f PFD the digital Σ-Δ modulator. For the third-order modulator used in the ADF4196, the repeat length depends on the value of MOD, as shown in Table 8. Table 8. Fractional Spurs with Dither Off Condition (Dither Off) MOD Is Divisible by 2 but Not by 3 ...
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... Initialization Sequence A includes Step 5A and omits Step 5B; Initialization Sequence B includes Step 5B and omits Step 5A. Two initialization sequences are available for the ADF4196: Initialization Sequence A and Initialization Sequence B. One or the other must be selected. Initialization Sequence A consists of Step 1 through Step 14 in Table 9, including Step 5A (but not Step 5B) ...
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... Tables of optimized FRAC and phase values for popular SW1/SW2 and I be downloaded from the ADF4196 product page. If using a phase table, first write the phase to double buffered Register R2, and then write the INT and FRAC values to Register R0. ...
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... NPO C0G capacitors are a good choice for this application tolerance is recommended for loop filter capacitors and 1% for resistors. A 10% tolerance is adequate for the inductor, L1. Rev Page timer = 28, the charge CP , should be set as low as possible good choice is to allow tune across the desired ADF4196 3 regulated P ...
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... GND GND 22 Figure 37. LO for DCS1800 Tx Using the Rev Page 18Ω 18Ω 10pF 18Ω 5.5V 100nF 10µF 100nF R3 62Ω 1.80kΩ OUT 470pF 30pF 2.2mH SIRENZA VCO190-1843T 38MHz/V ADF4196 Data Sheet 100pF RF OUT ...
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... When the third byte is written, bring the LE input high to complete the transfer. When power is first applied to the ADF4196, an initialization sequence is required for the output to become active (see Table 9). I/O port lines on the microcontroller are also used to detect lock (MUX configured as lock detect and polled by the port input) ...
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... EVAL-ADF4193EBZ1 EVAL-ADF4193EBZ2 Z = RoHS Compliant Part The EVAL-ADF4193EBZ1 and EVAL-ADF4193EBZ2 evaluation boards are designed to accommodate either the ADF4193 or the ADF4196. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09450-0-12/11(B) 5.00 BSC SQ ...