adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 24

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

ADF4196
Phase Lookup Table
The fast lock sequence of the
write to Register R0. The fast lock timers are programmed so
that after the PLL has settled into wide bandwidth mode, the
charge pump current is reduced and the loop filter resistor
switches are opened, which reduces the loop bandwidth. The
reference cycle on which these events occur is determined by
the values that are preprogrammed into the timeout counters.
The phase locking plots of Figure 11 and Figure 14 show that
the lock time to final phase is dominated by the phase swing
that occurs when the bandwidth is reduced. When the PLL
settles to its final frequency and phase, in wide bandwidth
mode, this phase swing is the same regardless of the size of the
frequency jump of the synthesizer. The amplitude of the phase
swing is related to the current flowing through the loop filter
resistors on the PFD reference cycle that open the SW1 and
SW2 switches.
In an integer-N PLL, this current is zero when the PLL has
settled. In a fractional-N PLL, the current is zero, on average,
but it varies from one reference cycle to the next, depending
on the quantization error sequence output from the digital Σ-Δ
modulator. Because the Σ-Δ modulator is all digital logic, clocked
at the PFD reference rate for a given value of MOD, the actual
quantization error on any given reference cycle is determined
by the value of FRAC and the phase word with which the
modulator is seeded, following the write to R0.
By choosing an appropriate value of phase corresponding to the
value of FRAC that is programmed on the next write to R0, the
size of the error current when the SW1 and SW2 switches are
opened can be minimized. Thus, the phase swing that occurs
when the bandwidth is reduced can be minimized.
With dither off, the fractional spur pattern that is due to the
quantization noise of the SDM also depends on the phase word
with which the modulator is seeded. Tables of optimized FRAC
and phase values for popular SW1/SW2 and I
be downloaded from the
table, first write the phase to double buffered Register R2, and
then write the INT and FRAC values to Register R0.
ADF4196
ADF4196
product page. If using a phase
is initiated after the
CP
timer settings can
Rev. B | Page 24 of 28
Avoiding Integer Boundary Channels
When programming a new frequency, another option involves
a write to Register R1 to avoid integer boundary spurs. If the
integer boundary spur level is too high, the integer boundary
can be moved away from the desired channel by reprogramming
the R divider to select a different PFD frequency. For example,
if REF
and MOD = 130 for 200 kHz steps, the frequency channel at
910.2 MHz has a 200 kHz integer boundary spur because it is
offset by 200 kHz from 35 × 26 MHz.
An alternative way to synthesize this channel is to set R = 5 for
a 20.8 MHz PFD reference and MOD = 104 for 200 kHz steps.
The 910.2 MHz channel becomes a 5 MHz offset from the nearest
integer multiple of 20.8 MHz, and the 5 MHz beat note spurs
are well attenuated by the loop. Setting the double buffered DB23
bit (Bit CP ADJ in Register R1) to 1 increases the charge pump
current by 25%, which compensates for the 25% increase in N
with the change to the 20.8 MHz PFD frequency. This maintains
constant loop dynamics and settling time performance for jumps
between the two PFD frequencies. Clear the CP ADJ bit when
returning to 26 MHz-based channels.
The Register R1 settings that are required for integer boundary
spur avoidance are all double buffered and do not become active
on the chip until the next write to Register R0. Always ensure that
Register R0 is the last register written to when programming
a new frequency.
Serial Interface Activity
The serial interface activity when programming the R2 or R1
register causes no noticeable disturbance to the synthesizer’s
settled phase or degradation in its frequency spectrum. Thus,
in a GSM application, serial interface activity can be performed
during the active part of the data burst. Because it takes only
10.2 µs to program the three registers (R2, R1, and R0) with the
6.5 MHz serial interface clock rate typically used, this program-
ming can also be performed during the previous guard period
with the LE edge to latch in the R0 data, delayed until it is time
to switch the frequency.
IN
= 104 MHz and R = 4 for a 26 MHz PFD reference,
Data Sheet