adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 11

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

Data Sheet
THEORY OF OPERATION
GENERAL DESCRIPTION
The
specifically to eliminate the need for ping-pong solutions.
It can also be used in pulse Doppler radar applications. The
ADF4196
bandwidth during a frequency change and narrowing the loop
bandwidth when frequency lock is achieved.
Widening the loop bandwidth is achieved by increasing the
charge pump current. To maintain stability with the changing
charge pump current, the
change the loop filter component values.
The narrow loop bandwidth ensures that phase noise and spur
specifications are met. A differential charge pump and loop filter
topology ensure that the fast lock time benefit obtained from
widening the loop bandwidth is maintained when the loop is
restored to narrow bandwidth mode for normal operation.
REFERENCE INPUT
The reference input stage is shown in Figure 20. Switch SW1
and Switch SW2 are normally closed, and Switch SW3 is
normally open. During power-down, SW3 is closed, and SW1
and SW2 are opened to ensure that there is no loading of the
REF
positive edge triggered PFD.
R Counter and Doubler
The 4-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the PFD.
A toggle flip-flop can be inserted after the R counter to provide
an additional divide-by-2. Using this option has the added
advantage of ensuring that the PFD reference clock has a 50/50
mark-to-space ratio. This ratio gives the maximum separation
between the fast lock timer clock, which is generated off the
falling edge of the PFD reference, and the rising edge, which is
the active edge in the PFD. It is recommended that this toggle
flip-flop be enabled for all even R divide values that are greater
than 2. The flip-flop must be enabled if dividing down a REF
frequency that is greater than 120 MHz.
An optional doubler before the 4-bit R counter can be used for
low REF
options, reference division ratios from 0.5 to 30 between REF
and the PFD are possible.
IN
ADF4196
pin. The falling edge of REF
IN
works on the basis of fast lock, using a wide loop
frequencies, up to 20 MHz. With these programmable
REF
IN
is targeted at GSM base station requirements,
NC
POWER-DOWN
Figure 20. Reference Input Stage
SW1
CONTROL
NO
NC
ADF4196
SW3
SW2
100kΩ
IN
includes switches that
is the active edge at the
BUFFER
TO R COUNTER
IN
Rev. B | Page 11 of 28
IN
RF INPUT STAGE
The RF input stage is shown in Figure 21. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the prescaler. Two prescaler options are available:
4/5 and 8/9. Select the 8/9 prescaler for N divider values that
are greater than 80.
RF N Divider
The RF N divider allows a fractional division ratio in the PLL
feedback path. The integer and fractional parts of the division
are programmed using separate registers, as shown in Figure 22
and described in the INT, FRAC, and MOD Relationship section.
Integer division ratios from 26 to 511 are allowed, and a third-
order Σ-Δ modulator interpolates the fractional value between
the integer steps.
INT, FRAC, and MOD Relationship
The INT, FRAC, and MOD values, programmed through the
serial interface, make it possible to generate RF output frequencies
that are spaced by fractions of the PFD reference frequency.
The N divider value, shown inside the brackets of the following
equation for the RF VCO frequency (RF
integer part (INT) and a fractional part (FRAC/MOD).
where:
RF
f
The value of MOD is chosen to give the desired channel step
with the available reference frequency. Then, program the INT
and FRAC words for the desired RF output frequency. See the
Worked Example section for more information.
PFD
INPUT STAGE
OUT
is the PFD reference frequency.
FROM RF
RF
is the output frequency of the external VCO.
OUT
RF
RF
= f
IN+
IN–
PFD
RF N DIVIDER
GENERATOR
N COUNTER
× [INT + (FRAC/MOD)]
Figure 22. Fractional-N RF Divider
VALUE
BIAS
INT
Figure 21. RF Input Stage
500Ω
1.6V
VALUE
MOD
N = INT + FRAC/MOD
500Ω
INTERPOLATOR
THIRD-ORDER
FRACTIONAL
OUT
), is composed of an
AGND
VALUE
AV
FRAC
DD
ADF4196
TO PFD
(1)