mc145201 Freescale Semiconductor, Inc, mc145201 Datasheet - Page 8

• Manufacturer Part Number: mc145201
• Description: 2.0 Ghz Pll Frequency Synthesizer
• Manufacturer: Freescale Semiconductor, Inc

DIGITAL INTERFACE PINS
D in
Serial Data Input (Pin 19)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the first buffer of the
R register, or 3 bytes (24 bits) to access the A register (see
Table 1). The values in the C, R, and A registers do not
change during shifting because the transfer of data to the
registers is controlled by ENB.
double–buffered. As indicated above, data is latched into the
first buffer on a 16–bit transfer. (The 3 MSBs are not double–
buffered and have an immediate effect after a 16–bit trans-
fer.) The second buffer of the R register contains the 13 bits
for the R counter. This second buffer is loaded with the con-
tents of the first buffer when the A register is loaded (a 24–bit
transfer). This allows presenting new values to the R, A, and
N counters simultaneously. If this is not required, then the
16–bit transfer may be followed by pulsing ENB low with no
signal on the CLK pin. This is an alternate method of
transferring data to the second buffer of the R register (see
Figure 17).
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the three registers.
Random access of any register is provided. That is, the reg-
isters may be accessed in any sequence. Data is retained in
the registers over a supply range of 4.5 to 5.5 V. The formats
are shown in Figures 15, 16, and 17.
immunity. This input can be directly interfaced to CMOS de-
vices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 k
to 10 k
the resistor are worst–case I OL of the driving device, maxi-
mum tolerable power consumption, and maximum data rate.
MC145201
8
Other Values
The bit stream begins with the most significant bit (MSB)
The 13 least significant bits (LSBs) of the R register are
The bit stream needs neither address nor steering bits due
D in typically switches near 50% of V DD to maximize noise
Values > 32
of Clocks
(MSBs are shifted in first; C0, R0, and A0 are the LSBs)
Number
The value programmed for the N–counter must be
greater than or equal to the value of the A–counter.
16
24
8
must be used. Parameters to consider when sizing
32
Table 1. Register Access
PIN DESCRIPTIONS
See Figure 13
See Figures
C Register
R Register
Accessed
A Register
Register
22–25
CAUTION
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
R15, R14, R13, . . ., R0
A23, A22, A21, . . ., A0
C7, C6, C5, . . ., C0
Nomenclature
Bit
CLK
Serial Data Clock Input (Pin 18)
D in pin, while high–to–low transitions shift bits from
OUTPUT A (when configured as Data Out, see Pin 16). The
24–1/2–stage shift register is static, allowing clock rates
down to dc in a continuous or intermittent mode.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty–four cycles are used to access the A regis-
ter. See Table 1 and Figures 15, 16, and 17. The number of
clocks required for cascaded devices is shown in Figures 24
through 26.
Schmitt–triggered input buffer. Slow CLK rise and fall times
are allowed. See the last paragraph of D in for more informa-
tion.
ENB
Active Low Enable Input (Pin 17)
transfer of data to/from the device. When ENB is in an inac-
tive high state, shifting is inhibited and the port is held in the
initialized state. To transfer data to the device, ENB (which
must start inactive high) is taken low, a serial transfer is
made via D in and CLK, and ENB is taken back high. The
low–to–high transition on ENB transfers data to the C or A
registers and first buffer of the R register, depending on the
data stream length per Table 1.
50% of V DD , thereby minimizing the chance of loading erro-
neous data into the registers. See the last paragraph of D in
for more information.
OUTPUT A
Configurable Digital Output (Pin 16)
A22 and A23 in the A register control the selection; see
Figure 16.
signal is the buffered output of the 13–stage R counter. The
f R signal appears as normally low and pulses high, and can
be used to verify the divide ratio of the R counter. This ratio
extends from 5 to 8191 and is determined by the binary value
loaded into bits R0 through R12 in the R register. Also, direct
access to the phase detectors via the REF in pin is allowed by
choosing a divide value of 1 (see Figure 17). The maximum
frequency at which the phase detectors operate is 2 MHz.
Therefore, the frequency of f R should not exceed 2 MHz.
Low–to–high transitions on CLK shift bits available at the
Eight clock cycles are required to access the C register.
CLK typically switches near 50% of V DD and has a
This pin is used to activate the serial interface to allow the
This input is also Schmitt–triggered and switches near
For POR information, see the note for the CLK pin.
OUTPUT A is selectable as f R , f V , Data Out, or Port. Bits
If A23 = A22 = high, OUTPUT A is configured as f R . This
To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
GND (with ENB being a don’t care) or ENB must
be held at the potential of the V+ pin (with CLK be-
ing a don’t care) during power–up. As an alterna-
tive, the bit sequence of Figure 13 may be used.
Transitions on ENB must not be attempted while
CLK is high. This puts the device out of synchro-
nization with the microcontroller. Resynchroniza-
tion occurs when ENB is high and CLK is low.
MOTOROLA WIRELESS SEMICONDUCTOR
NOTE
NOTE
SOLUTIONS DEVICE DATA