74lv86db NXP Semiconductors, 74lv86db Datasheet

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74lv86db

Manufacturer Part Number
74lv86db
Description
Quad 2-input Exclusive-or Gate
Manufacturer
NXP Semiconductors
Datasheet
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74LV86N
74LV86D
74LV86DB
74LV86PW
74LV86BQ
Ordering information
Package
Temperature range Name
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74LV86 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC86 and 74HCT86.
The 74LV86 provides a quad 2-input exclusive-OR function.
74LV86
Quad 2-input exclusive-OR gate
Rev. 03 — 27 November 2007
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
Typical output ground bounce < 0.8 V at V
Typical HIGH-level output voltage (V
T
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
amb
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
= 25 C
DIP14
SO14
SSOP14
TSSOP14
DHVQFN14 plastic dual in-line compatible thermal enhanced very
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
thin quad flat package; no leads; 14 terminals;
body 2.5
3
CC
OH
0.85 mm
) undershoot: > 2 V at V
= 2.7 V and V
CC
= 3.3 V and T
CC
= 3.6 V
amb
= 25 C
CC
Product data sheet
= 3.3 V and
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
SOT762-1

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74lv86db Summary of contents

Page 1

... Specified from +85 C and from +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LV86N +125 C 74LV86D +125 C 74LV86DB +125 C 74LV86PW +125 C 74LV86BQ +125 Description DIP14 plastic dual in-line package; 14 leads (300 mil) SO14 plastic small outline package ...

Page 2

... NXP Semiconductors 4. Functional diagram mna787 Fig 1. Logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning GND 7 001aad103 Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 74LV86_3 ...

Page 3

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin GND Functional description Table 3. Function table H = HIGH voltage level LOW voltage level Input Limiting values Table 4 ...

Page 4

... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter P total power dissipation tot DIP14 package SO14 package (T)SSOP14 package DHVQFN14 package [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. ...

Page 5

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I supply current CC I additional supply current ...

Page 6

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions t propagation delay nA nY; see power dissipation capacitance V I [1] All typical values are measured the same as t and t ...

Page 7

... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. The input (nA, nB) to output (nY) propagation delays Table 8. Measurement points Supply voltage V CC < 2 3.6 V 4.5 V Test data is given in Table 9. Defi ...

Page 8

... NXP Semiconductors 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 9

... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 10 ...

Page 11

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 13

... Document ID Release date 74LV86_3 20071127 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...

Page 14

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Abbreviations ...

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