ad8318acpz-wp Analog Devices, Inc., ad8318acpz-wp Datasheet - Page 22

• Manufacturer Part Number: ad8318acpz-wp
• Description: 1 Mhz To 8 Ghz, 70 Db Logarithmic Detector/controller
• Manufacturer: Analog Devices, Inc.

AD8318
EVALUATION BOARD
Table 6. Evaluation Board (Rev. A) Bill of Materials
Component
VP, GND
SW1, R3
R1, C1, C2
R2
R4
R7, R8, R9, R10
R7, R8, R9, R10
C5, C6, C7, C8, R5, R6
C9
Function
Supply and Ground Connections
Device Enable. When in Position A, the ENBL pin is connected to VP and the
AD8318 is in operating mode. In Position B, the ENBL pin is grounded through
R3, putting the device in power-down mode. The ENBL pin may be exercised
by a pulse generator connected to ENBL SMA and SW1 in Position B.
Input Interface. The 52.3 Ω resistor (R1) combines with the AD8318 internal
input impedance to give a broadband input impedance of 50 Ω. C1 and C2 are
dc-blocking capacitors. A reactive impedance match can be implemented by
replacing R1 with an inductor and C1 and C2 with appropriately valued
capacitors.
Temperature Sensor Interface. The temperature sensor output voltage is
available at the SMA labeled TEMP via the current limiting resistor, R2.
Temperature Compensation Interface. The internal temperature compensation
resistor is optimized for an input signal of 2.2 GHz when R4 is 500 Ω. This circuit
can be adjusted to optimize performance for other input frequencies by
changing the value of Resistor R4. See the Temperature Compensation of
Output Voltage section.
Output Interface—Measurement Mode. In measurement mode, a portion of
the output voltage is fed back to the VSET pin via R7. The magnitude of the
slope at VOUT can be increased by reducing the portion of V
to VSET. R10 can be used as a back-terminating resistor or as part of a single-
pole, low-pass filter.
Output Interface—Controller Mode. In this mode, R7 must be open. In
controller mode, the AD8318 can control the gain of an external component. A
setpoint voltage is applied to the VSET pin, the value of which corresponds to
the desired RF input signal level applied to the AD8318 RF input. The
magnitude of the control voltage is optionally attenuated via the voltage
divider comprised of R8 and R9, or a capacitor can be installed in R8 to form a
low-pass filter along with R9. See the Controller Mode section for more details.
Power Supply Decoupling. The nominal supply decoupling consists of a 100 pF
filter capacitor placed physically close to the AD8318, a 0 Ω series resistor, and
a 0.1 μF capacitor placed closer to the power supply input pin.
Loop Filter Capacitor. The low-pass corner frequency of the circuit that drives
the VOUT pin can be lowered by placing a capacitor between CLPF and
ground. Increasing this capacitor increases the overall rise/fall time of the
AD8318 for pulsed input signals. See the Output Filtering section for more details.
Rev. B | Page 22 of 24
OUT
that is fed back
Default Conditions
Not Applicable
SW1 = A
R3 = 10 kΩ (Size 0603)
R1 = 52.3 Ω (Size 0402)
C1 = 1 nF (Size 0402)
C2 = 1 nF (Size 0402)
R2 = 1 kΩ (Size 0402)
R4 = 499 Ω (Size 0603)
R7 = 0 Ω = (Size 0402)
R8 = open (Size 0402)
R9 = open (Size 0402
R10 = 0 Ω (Size 0402)
R7 = open (Size 0402)
R8 = open (Size 0402)
R9 = 0 Ω (Size 0402)
R10 = 0 Ω (Size 0402)
C5 = 0.1 μF (Size 0603)
C6 = 100 pF (Size 0402)
C7 = 100 pF (Size 0402)
C8 = 0.1 μF (Size 0603)
R5 = 0 Ω (Size 0603)
R6 = 0 Ω (Size 0603)
C9 = open (Size 0603)