pcf8582c NXP Semiconductors, pcf8582c Datasheet

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pcf8582c

Manufacturer Part Number
pcf8582c
Description
Pcf8582c-2 256 X 8-bit Cmos Eeprom With I2c-bus Interface
Manufacturer
NXP Semiconductors
Datasheet

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1. Description
2. Features
The PCF8582C-2 is a floating gate Electrically Erasable Programmable Read Only
Memory (EEPROM) with 2 kbits (256
internal redundant storage code, it is fault tolerant to single bit errors. This feature
dramatically increases the reliability compared to conventional EEPROMs. Power
consumption is low due to the full CMOS technology used. The programming voltage
is generated on-chip, using a voltage multiplier.
Data bytes are received and transmitted via the serial I
PCF8582C-2 devices may be connected to the I
by three address inputs (A0, A1 and A2).
Timing of the E/W cycle is carried out internally, thus no external components are
required. Programming Time Control (PTC), Pin 7, must be connected to either V
or left open-circuit. There is an option of using an external clock for timing the length
of an E/W cycle.
PCF8582C-2
256
Rev. 04 — 25 October 2004
Low power CMOS:
Non-volatile storage of 2 kbits organized as 256
Single supply with full operation down to 2.5 V
On-chip voltage multiplier
Serial input/output I
Write operations:
Read operations:
Internal timer for writing (no external components)
Internal power-on reset
0 kHz to 100 kHz clock frequency
High reliability by using a redundant storage code
Endurance: 1,000,000 Erase/Write (E/W) cycles at T
10 years non-volatile data retention time
2.0 mA maximum operating current
maximum standby current 10 A (at 6.0 V), typical 4 A
byte write mode
8-byte page write mode (minimizes total write time per byte)
sequential read
random read
8-bit CMOS EEPROM with I
2
C-bus
8-bit) non-volatile storage. By using an
2
2
C-bus. Chip select is accomplished
C-bus interface
8-bit
2
C-bus. Up to eight
amb
= 22 C
Product data
DD

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pcf8582c Summary of contents

Page 1

... Rev. 04 — 25 October 2004 1. Description The PCF8582C floating gate Electrically Erasable Programmable Read Only Memory (EEPROM) with 2 kbits (256 internal redundant storage code fault tolerant to single bit errors. This feature dramatically increases the reliability compared to conventional EEPROMs. Power consumption is low due to the full CMOS technology used ...

Page 2

... V DD Ordering information Package Name Description DIP8 plastic dual in-line package; 8 leads (300 mil) SO8 plastic small outline package 8 leads (straight); body width 3.9 mm Ordering options Topside mark PCF8582C-2 8582C-2 Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface Min Typ Max Unit 2.5 - 6.0 ...

Page 3

... PCF8582C-2 6 SCL INPUT 5 FILTER SDA n ADDRESS SHIFT SWITCH REGISTER TEST MODE DECODER POWER-ON-RESET Fig 1. Block diagram C-BUS CONTROL LOGIC ADDRESS BYTE HIGH COUNTER REGISTER ...

Page 4

... The Most Significant Bit (MSB) ‘b7’ is sent first. A2, A1, A0 are hardware selectable pins. A system could have up to eight PCF8582C-2 devices on the same I equivalent kbit EEPROM or 8 pages of 256 bytes of memory. The eight addresses are defined by the state of the A0, A1, A2 inputs (logic level ‘1’ ...

Page 5

... C-BUS 256-BYTE PAGE PCF8582C-2 DEVICE 2 256-BYTE PAGE PCF8582C-2 DEVICE 3 256-BYTE PAGE PCF8582C-2 DEVICE 4 256-BYTE PAGE PCF8582C-2 DEVICE 5 256-BYTE PAGE PCF8582C-2 DEVICE 6 256-BYTE PAGE PCF8582C-2 DEVICE 7 256-BYTE PAGE PCF8582C-2 DEVICE 8 256-BYTE PAGE 002aaa246 Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface ...

Page 6

... Data transfer is unlimited in the read mode. The information is transmitted in bytes and each receiver acknowledges with a ninth bit. Within the I fast speed mode (400 kHz clock rate) are defined. The PCF8582C-2 operates in only the standard-speed mode. By definition, a device that sends a signal is called a ‘transmitter’, and the device which receives the signal is called a ‘ ...

Page 7

... Byte/word write: field. This address field is a word address providing access to the 256 words of memory. Upon receipt of the word address, the PCF8582C-2 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. Word address is automatically incremented. The master can now terminate the transfer by generating a STOP condition or transmit up to six more bytes of data and then terminate by generating a STOP condition ...

Page 8

... Fig 5. Auto-increment memory word address; two byte write. Page write: initiated in the same manner as the byte write operation. The master can transit eight data bytes within one transmission. After receipt of each byte, the PCF8582C-2 will respond with an acknowledge. The typical E/W time in this mode ...

Page 9

... S SLAVE ADDRESS 0 A R/W Fig 7. Master reads PCF8582C-2 slave after setting word address (write word address; read data); sequential read. S SLAVE ADDRESS Fig 8. Master reads PCF8582C-2 immediately after first byte (read mode); current address read. 9397 750 14222 Product data ...

Page 10

... 6 100 kHz SCL 0.8 0.9V DD 0.8 0. Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface Max Unit +6 +150 C +85 C Typ Max Unit - 6 200 ...

Page 11

... CMOS EEPROM with I Conditions Min 0 DD(min amb ; see Figure 9. DD Conditions repeated start Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface Typ Max Unit - years and V IL Min Max Unit 0 100 kHz 4 ...

Page 12

... HD;DAT SU;DAT 2 C-bus. Conditions internal oscillator external clock +85 C amb amb HIGH t LOW 1 2 STOP Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface t HD;STA SU;STA SU;STO MBA705 Min Typ Max 100000 1000000 ...

Page 13

... HIGH t LOW 1 2 STOP HIGH t LOW 1 2 STOP A DATA A DATA negative edge SCL 8-bit Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface n x 256 + 1 MBA698 1153 MBA699 A P (1) undefined 1 2 257 clock ( 513 clock ( 1153 clock (4) ...

Page 14

... 0.53 1.07 0.36 9.8 6.48 2.54 0.38 0.89 0.23 9.2 6.20 0.021 0.042 0.014 0.39 0.26 0.1 0.015 0.035 0.009 0.36 0.24 REFERENCES JEDEC JEITA MO-001 SC-504-8 Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface SOT97 ( max. 3.60 8.25 10.0 7.62 0.254 1.15 3.05 7.80 8.3 0.14 0.32 0.39 0.3 0.01 0.045 0.12 0.31 0.33 EUROPEAN ISSUE DATE ...

Page 15

... 0.25 5.0 4.0 6.2 1.27 1.05 0.19 4.8 3.8 5.8 0.0100 0.20 0.16 0.244 0.05 0.041 0.0075 0.19 0.15 0.228 REFERENCES JEDEC JEITA MS-012 Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface SOT96 detail X ( 1.0 0.7 0.7 0.25 0.25 0.1 0.4 0.6 0.3 0.039 0.028 0.028 0.01 0.01 0.004 ...

Page 16

... C (SnPb process) or below 245 C (Pb-free process) – for all the BGA and SSOP-T packages 9397 750 14222 Product data 256 8-bit CMOS EEPROM with I Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface ). stg(max) © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 17

... When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 9397 750 14222 Product data 256 8-bit CMOS EEPROM with I 2 called small/thin packages. Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface 3 350 mm so called © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 18

... DHVQFN, HBCC, HBGA, not suitable HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS [7] PLCC , SO, SOJ suitable LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO, not recommended VSSOP Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface [2] Reflow Dipping [3] suitable not suitable suitable [6] suitable suitable [7][8] ...

Page 19

... Product data; initial version (as PCF85xxC-2 family , 9397 750 01773). 01 19970213 - 9397 750 14222 Product data 256 8-bit CMOS EEPROM with I 6, third paragraph: change ‘high-speed’ to Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 20

... Licenses Purchase of Philips I Rev. 04 — 25 October 2004 PCF8582C-2 2 C-bus interface 2 C components 2 Purchase of Philips I ...

Page 21

... Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 25 October 2004 Document order number: 9397 750 14222 PCF8582C-2 256 8-bit CMOS EEPROM with I 2 C-bus interface ...

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