pca8576c NXP Semiconductors, pca8576c Datasheet
pca8576c
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pca8576c Summary of contents
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... Universal LCD driver for low multiplex rates Rev. 1 — 22 July 2010 1. General description The PCA8576C is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and segments and can easily be cascaded for larger LCD applications. The PCA8576C is compatible with most ...
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... SYNC OSC OSCILLATOR POWER- RESET V SS SCL INPUT FILTERS SDA Fig 1. Block diagram of PCA8576C PCA8576C Product data sheet Ordering information Package Name Description LQFP64 plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm Marking codes BP0 BP2 BP1 BP3 BACKPLANE ...
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... SYNC 12 CLK OSC 16 A0 Top view. For mechanical details, see Pin configuration for LQFP64 (PCA8576CH/Q900/1) All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates PCA8576CH Figure 29. 48 n.c. 47 S17 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates Description 2 I C-bus serial data input and output 2 I C-bus serial clock input ...
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... LCD segment or dot matrix displays (see Figure backplanes and segments. Fig 3. The possible display configurations of the PCA8576C depend on the number of active backplane outputs required. A selection of display configurations is shown in of these configurations can be implemented in the typical system shown in Table 4. Number of ...
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... The internal oscillator is selected by connecting pin OSC to V power supplies (pins V 7.1 Power-On-Reset (POR) At power-on the PCA8576C resets to the following starting conditions: • All backplane and segment outputs are set to V • The selected drive mode is 1:4 multiplex with • ...
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... RMS ------------------------------------------- - = – – All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates Table off RMS on RMS ------------------------ - ----------------------- - V V LCD LCD 0 1 0.354 0.791 0.333 0.745 ...
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... LCD LCD off RMS is sometimes referred as the LCD operating voltage. LCD All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates V = 2.449V ( ) ( ) off RMS off RMS × 2.309V ...
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... V (t). state2 Sn+1 BP0 off(RMS) Static drive mode waveforms All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates Figure T fr LCD segments state 1 state 2 (on) (off) mgl745 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA8576C allows the use of Fig 6. PCA8576C Product data sheet ⁄ 1 bias LCD BP0 LCD LCD BP1 LCD LCD ...
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... BP1 V = 0.333V off(RMS) LCD. Waveforms for the 1:2 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms mgl747 at LCD segment ...
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... Sn BP1 V = 0.333V off(RMS) LCD. Waveforms for the 1:3 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (b) Resultant waveforms mgl748 at LCD segment. ...
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... V (t). state2 Sn BP1 V = 0.333V off(RMS) LCD. Waveforms for the 1:4 multiplex mode with All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates T fr state 1 state 2 mgl749 at LCD segment. ⁄ 1 bias 3 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCA8576C are timed by the frequency f , which equals either the built-in oscillator frequency f clk f . clk(ext) The clock frequency (f for data reception from the I rate of 100 kHz, f 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin V output from pin CLK is the clock signal for any cascaded PCA8576C in the system ...
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... PCA8576C Product data sheet Universal LCD driver for low multiplex rates All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C 2 C-bus. When a device is unable to 2 C-bus © NXP B.V. 2010. All rights reserved. ...
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... BP3 respectively. Fig 10. Display RAM bit map When display data is transmitted to the PCA8576C, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples or quadruples ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCA8576C occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character ...
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... In the static mode: row 0 is selected. The PCA8576C includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row selected for display instead of the contents of row 0. In 1:2 multiplex drive mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1 ...
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... Table 9). 2 C-bus SDA SCL data line stable; data valid S START condition All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Figure 12. change of data allowed mba607 Figure 13. P STOP condition © NXP B.V. 2010. All rights reserved. SDA ...
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... Acknowledgement on the I PCA8576C Product data sheet MASTER SLAVE TRANSMITTER/ RECEIVER RECEIVER 2 C-bus is illustrated in All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates SLAVE MASTER TRANSMITTER/ TRANSMITTER RECEIVER Figure 15. MASTER TRANSMITTER/ RECEIVER mga807 © ...
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... A0, A1, and A2 are tied to V devices with a common I In the power-saving mode it is possible that the PCA8576C is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. If this situation occurs, the PCA8576C forces the SCL line LOW until its internal operations are completed ...
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... RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data is directed to the intended PCA8576C device. The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed PCA8576C. After the last display byte, the I Fig 16 ...
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... The possibility to disable the display allows implementation of blinking under external control. [2] Bit B is not applicable for the static LCD drive mode. 7.18.2 Load-data-pointer command Table 10. Bit PCA8576C Product data sheet Definition of PCA8576C commands Operation Code P[5:0] ...
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... Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. 7.19 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCA8576C and coordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. ...
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... Universal LCD driver for low multiplex rates V LCD V SS SDA, SCL CLK, OSC A2, SA0, SYNC V DD All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C BP0 to BP3 S39 013aaa109 © NXP B.V. 2010. All rights reserved ...
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... DD Ref. 8 “JESD78” All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. LCD DD Min − ...
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... output sink current 0 5 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates ° C; unless otherwise specified. Min Typ 2.0 - − 6.0 [ [2] ...
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... mbe530 −I DD(LCD) power-saving mode 200 f (Hz °C Fig 20. −I All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates ° C; unless otherwise specified. Min Typ −20 - − C-bus inactive ...
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... Fig 22. −I mbe532 R O(max) (kΩ (V) DD Fig 24 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates ° °C 20 −40 ° ° ...
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... power-saving mode LCD Figure 26) . All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates ° +85 C; unless otherwise specified. Min Typ [1] 125 200 ...
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... Product data sheet 1/f CLK t clk(H) CLK SYNC t PD(SYNC_N BUF LOW t HD;STA 2 C-bus timing waveforms All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates t clk(L) t PD(SYNC_N) t SYNC_NL t PD(drv HD;DAT t HIGH t SU ...
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... NXP Semiconductors 12. Application information 12.1 Cascaded operation In large display configurations PCA8576Cs can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable 2 I C-bus slave address (SA0). Table 17. Cluster 1 2 Cascaded PCA8576Cs are synchronized. They can share the backplane signals from one of the devices in the cascade ...
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... A PCA8576C asserts the SYNC line and monitors the SYNC line at all other times. If synchronization in the cascade is lost restored by the first PCA8576C to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCA8576C are shown in PCA8576C ...
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... NXP Semiconductors Fig 28. Synchronization of the cascade for the various PCA8576C drive modes PCA8576C Product data sheet BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. ...
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... UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT314-2 136E10 Fig 29. Package outline SOT314-2 (LQFP64) of PCA8576CH PCA8576C Product data sheet ...
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... Inspection and repair • Lead-free soldering versus SnPb soldering PCA8576C Product data sheet Universal LCD driver for low multiplex rates All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C © NXP B.V. 2010. All rights reserved ...
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... Volume (mm ) < 350 260 260 250 Figure 30. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates Figure 30) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 ...
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... MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates peak temperature © NXP B.V. 2010. All rights reserved. time 001aac844 ...
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... Random Access Memory Root Mean Square Serial Clock Line Serial DAta line Surface-Mount Device All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... NX3-00092 — NXP store and transport requirements [10] SNV-FA-01-02 — Marking Formats Integrated Circuits [11] UM10204 — I 18. Revision history Table 21. Revision history Document ID Release date PCA8576C v.1 20100722 PCA8576C Product data sheet Universal LCD driver for low multiplex rates 2 C-bus specification and user manual Data sheet status ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2010 PCA8576C Universal LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... Package outline Handling information . . . . . . . . . . . . . . . . . . . 37 Soldering of SMD packages . . . . . . . . . . . . . . 37 Introduction to soldering Wave and reflow soldering Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 38 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 38 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40 References Revision history . . . . . . . . . . . . . . . . . . . . . . . 41 Legal information . . . . . . . . . . . . . . . . . . . . . . 42 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Contact information . . . . . . . . . . . . . . . . . . . . 43 Contents Date of release: 22 July 2010 Document identifier: PCA8576C All rights reserved. ...