adc1004s030 NXP Semiconductors, adc1004s030 Datasheet
adc1004s030
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adc1004s030 Summary of contents
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... Single 10 bits ADC MHz, 40 MHz or 50 MHz Rev. 03 — 7 August 2008 1. General description The ADC1004S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital Converters (ADC) for professional video and other applications. They convert the analog input signal into 10-bit binary-coded digital signals at a maximum sampling rate of 50 MHz ...
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... MHz; clk ramp input differential non-linearity MHz; clk ramp input maximum clock frequency ADC1004S030TS ADC1004S040TS ADC1004S050TS total power dissipation MHz; clk ramp input Description plastic shrink small outline package; 28 leads; body width 5.3 mm plastic shrink small outline package; 28 leads; ...
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... Fig 1. Block diagram ADC1004S030_040_050_3 Product data sheet Single 10 bits ADC MHz, 40 MHz or 50 MHz CLK 1 CLOCK DRIVER LATCHES CONVERTER IN-RANGE LATCH 12 DGND2 digital ground Rev. 03 — 7 August 2008 ADC1004S030/040/050 V OE CCD2 CMOS 20 D4 OUTPUTS 19 ...
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... output ground 15 not connected 16 data output; bit 0 (Least Significant Bit (LSB)) 17 data output; bit 1 18 data output; bit 2 19 data output; bit 3 Rev. 03 — 7 August 2008 ADC1004S030/040/050 28 V CCD1 27 DGND1 ...
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... DGND output current storage temperature ambient temperature junction temperature , V and V may have any value between 0.3 V and +7.0 V provided that CCA CCD CCO are respected. CC Thermal characteristics Parameter thermal resistance from junction to ambient Rev. 03 — 7 August 2008 ADC1004S030/040/050 Min Max [1] 0.3 +7.0 [1] 0.3 +7.0 [1] 0.3 +7.0 V 0.1 +1.0 CCD V 0.1 +4 ...
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... Table 4.43 MHz - i - Table 7 1 Rev. 03 — 7 August 2008 ADC1004S030/040/050 = +70 C; typical values measured at amb Typ Max 5.0 5.25 5.0 5.25 3.3 5.25 0.20 - +0.20 0.20 - +2.25 0.20 - +2. 175 247 - 0 CCD 0.8 - ...
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... [4] from device to device 1 3. [5] full-scale sine wave - 75 % full-scale sine - wave small signal at - mid-scale LSB at code I 512 Rev. 03 — 7 August 2008 ADC1004S030/040/050 = +70 C; typical values measured at amb Typ Max 245 - 456 - 175 - 175 - 2.02 2.55 - 0.5 0 CCO CCO 20 - +20 - ...
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... MHz MHz MHz MHz clk MHz; clk f = 4.43 MHz LSB at code I 512 MHz; clk PAL modulated ramp Rev. 03 — 7 August 2008 ADC1004S030/040/050 = +70 C; typical values measured at amb Min Typ Max [6] - 1.5 3.0 - 1.5 3 ...
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... --------------------------------------- - and its variation with temperature and supply voltage. When several ADCs are RT RB 100 Rev. 03 — 7 August 2008 ADC1004S030/040/050 = +70 C; typical values measured at amb Min Typ Max - 0 5.5 8.5 - ...
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... Rev. 03 — 7 August 2008 ADC1004S030/040/050 . For 50 MHz version NXP Semicocnductors d(max code 1023 lad R L code 014aaa325 Two’s complement ...
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... N sample w(clk)L t w(clk)H CLK sample N sample d(s) DATA DATA DATA Timing diagram Rev. 03 — 7 August 2008 ADC1004S030/040/050 IR high impedance active active 1 sample sample h(o) DATA DATA d(o) 014aaa326 © NXP B.V. 2008. All rights reserved. V ...
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... ADC1004S050 frequency on pin OE = 100 kHz Timing diagram and test conditions of 3-state output delay time t s(LH) code 1023 V 50% I code CLK 50% Analog input settling time diagram Rev. 03 — 7 August 2008 ADC1004S030/040/050 50 dHZ dZH HIGH 90% LOW t dZL 50% TEST V CCD t dLZ t dZL ...
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... Fig 8. Typical fast Fourier transform (f ADC1004S030_040_050_3 Product data sheet Single 10 bits ADC MHz, 40 MHz or 50 MHz 5.00 10 MHz 4.43 MHz) clk i 10 MHz MHz) clk i Rev. 03 — 7 August 2008 ADC1004S030/040/050 15.0 f (MHz) 15.0 20.0 f (MHz) © NXP B.V. 2008. All rights reserved. 014aaa328 20.0 014aaa329 25 ...
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... NXP Semiconductors Fig 9. CMOS data and in-range outputs V CCO OE TC OGND Fig 11. OE and TC input Fig 13. CLK input ADC1004S030_040_050_3 Product data sheet ADC1004S030/040/050 Single 10 bits ADC MHz, 40 MHz or 50 MHz V CCA V CCO OGND AGND 014aaa330 Fig 10. Analog inputs ...
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... AGND The analog and digital supplies should be separated and well decoupled A user manual is available that describes the demonstration board that uses the version ADC1004S030/040/050 family with an application environment. (1) RB, RM and RT are decoupled to AGND. (2) Pin 15 may be connected to DGND in order to prevent noise influence. ...
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... Single 10 bits ADC MHz, 40 MHz or 50 MHz 2.5 scale (1) ( 0.38 0.20 10.4 5.4 7.9 0.65 0.25 0.09 10.0 5.2 7.6 REFERENCES JEDEC JEITA MO-150 Rev. 03 — 7 August 2008 ADC1004S030/040/050 detail 1.03 0.9 1.25 0.2 0.13 0.63 0.7 EUROPEAN PROJECTION SOT341 ...
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... Data sheet status Product data sheet Corrections made to the table description in Corrections made to several entries in Corrections made to Figure 12. Product data sheet Product data sheet Rev. 03 — 7 August 2008 ADC1004S030/040/050 Change notice Supersedes - ADC1004S030_040_050_2 Table 1. Table 6. - ADC1004S030_040_050_1 - - © NXP B.V. 2008. All rights reserved ...
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... Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 7 August 2008 ADC1004S030/040/050 © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 7 August 2008 Document identifier: ADC1004S030_040_050_3 ...