ad1870arz-reel Analog Devices, Inc., ad1870arz-reel Datasheet - Page 15

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ad1870arz-reel

Manufacturer Part Number
ad1870arz-reel
Description
Single-supply 16-bit Stereo Adc
Manufacturer
Analog Devices, Inc.
Datasheet
REV. A
RDEDGE = LO
RDEDGE = LO
RDEDGE = HI
RDEDGE = HI
RDEDGE = LO
RDEDGE = HI
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Figure 10. Serial Data Output Timing: Slave Mode, I
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
WCLK
LRCK
BCLK
BCLK
SOUT
WCLK
Figure 11. Serial Data Output Timing: Master Mode, Right-Justified with No MSB Delay, S/ M = LO,
R L JUST = Hl, MSBDLY = Hl
BCLK
BCLK
SOUT
LRCK
TAG
INPUT
INPUT
WCLK
LRCK
BCLK
BCLK
SOUT
TAG
TAG
PREVIOUS DATA
MSB-14
PREVIOUS DATA
MSB-14
Figure 12. Serial Data Output Timing: Master Mode, Right-Justified with MSB Delay,
WCLK Pulsed in 17th BCLK Cycle, S/ M = LO, R L JUST = Hl, MSBDLY = LO
31
32
ZEROS
LSB
LSB
MSB
32
32
LEFT TAG
1
LEFT TAG
MSB
MSB
LSB
LEFT TAG
1
1
2
ZEROS
MSB
LSB
LSB
2
2
LEFT DATA
MSB-1
3
ZEROS
15
MSB-2
16
4
16
17
5
MSB
MSB
17
18
LEFT DATA
LEFT DATA
MSB-1
MSB-1
LSB
18
17
19
MSB-2
MSB-2
19
20
–15–
2
S-Justified, S/ M = Hl, R L JUST = LO, MSBDLY = LO
LSB
LSB
MSB
32
RIGHT TAG
1
MSB
RIGHT TAG
LSB
1
31
ZEROS
2
ZEROS
ZEROS
LSB
2
32
RIGHT TAG
MSB
15
1
16
MSB
LSB
16
17
2
RIGHT DATA
MSB-1
MSB
MSB
17
3
18
RIGHT DATA
RIGHT DATA
MSB-2
MSB-1 MSB-2
MSB-1 MSB-2
18
19
4
19
5
20
LSB
17
LSB
LSB
32
1
AD1870
ZEROS
MSB
LEFT TAG
1
ZEROS
2
ZEROS
LSB
2

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