ad1870arz-reel Analog Devices, Inc., ad1870arz-reel Datasheet - Page 9

• Manufacturer Part Number: ad1870arz-reel
• Description: Single-supply 16-bit Stereo Adc
• Manufacturer: Analog Devices, Inc.

REV. A
The AD1870 achieves its specified performance without the
need for user trims or adjustments. This is accomplished through
the use of on-chip automatic offset calibration that takes place
immediately following reset. This procedure nulls out any off-
sets in the single-to-differential converter, the analog modulator,
and the decimation filter. Autocalibration completes in approxi-
mately 8192 × (1/(F
once at power-up in most applications. (In Slave Mode, the 8192
cycles required for autocalibration do not start until after the
first rising edge of LRCK following the first falling edge of
LRCK.) The autocalibration scheme assumes that the inputs
are ac-coupled. DC-coupled inputs will work with the AD1870,
but the autocalibration algorithm will yield an incorrect offset
compensation.
The AD1870 also features a Power-Down Mode. It is enabled
by the active LO RESET Pin 23 (i.e., the AD1870 is in Power-
Down Mode while RESET is held LO). The power savings are
specified in the Specifications section. The converter is shut
down in the power-down state and will not perform conversions.
The AD1870 will be reset upon leaving the power-down state, and
autocalibration will commence after the RESET pin goes HI.
Power consumption can be further reduced by slowing down the
master clock input (at the expense of input pass band width).
Note that a minimum clock frequency, f
the AD1870.
TAG Overrange Output
The AD1870 includes a TAG serial output (Pin 27) that is pro-
vided to indicate status on the level of the input voltage. The
TAG output is at TTL compatible logic levels. A pair of unsigned
binary bits are output, synchronous with LRCK (MSB then
LSB), that indicate whether the current signal being converted
is: more than 1 dB under full scale, within 1 dB under full scale,
within 1 dB over full scale, or more than 1 dB over full scale.
The timing for the TAG output is shown in Figures 7–16. Note
that the TAG Bits are not “sticky”; i.e., they are not peak read-
ing, but rather change with every sample. Decoding of these two
bits is as follows:
TAG
MSB
0
0
1
1
Bits
LSB
0
1
0
1
L
R
CK
Meaning
More than 1 dB under Full Scale
Within 1 dB under Full Scale
Within 1 dB over Full Scale
More Than 1 dB over Full Scale
) seconds and need only be performed
CLKIN
, is specified for
–9–
APPLICATION ISSUES
Recommended Input Structure
The AD1870 input structure is single-ended to allow the board
designer to achieve a high level of functional integration. The
very simple recommended input circuit is shown in Figure 2. Note
the 1 µF ac-coupling capacitor, which allows input level shifting
for 5 V only operation and for autocalibration to properly null
offsets. The 3 dB point of the single-pole antialias RC filter is
240 kHz, which results in essentially no attenuation at 20 kHz.
Attenuation at 3 MHz is approximately 22 dB, which is adequate
to suppress f
nally ac-coupled, the 1 µF ac-coupling capacitors shown in
Figure 2 are not required.
Analog Input Voltage Swing
The single-ended input range of the analog inputs is specified in
relative terms in the Specifications section. The input level at
which clipping occurs linearly tracks the voltage reference
level; i.e., if the reference is high relative to the typical 2.25
V, the allowable input range without clipping is correspondingly
wider, and if the reference is low relative to the typical 2.25 V,
the allowable input range is correspondingly narrower.
Thus the maximum input voltage swing can be computed using
the following ratio:
2 983
.
2 25
Figure 2. Recommended Input Structure for Externally
DC-Coupled Inputs
.
V p
V Nominal Reference Voltage
(
−
p Nominal Voltage Swing
RIGHT
INPUT
INPUT
(
LEFT
S
noise modulation. If the analog inputs are exter-
300
300
)
)
2.2nF
NPO
2.2nF
NPO
=
Y V Maximum Swing Without Clipping
X V Measured Referenc Voltage
1 F
1 F
(
(
V
V
AD1870
IN
IN
L
R
AD1870
e
)
)