tda8296 NXP Semiconductors, tda8296 Datasheet - Page 47

• Manufacturer Part Number: tda8296
• Description: Tda8296 Digital Global Standard Low If Demodulator For Analog Tv And Fm Radio
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8296
Product data sheet
9.3.18 GPIOs
For optimum performances, the following relations must be respected:
In the TDA8296, three general purpose input/outputs are implemented.
Table 54.
Legend: * = default value.
Table 55.
Legend: * = default value.
Bit
7 to 4 GP1_CF[3:0]
3 to 0 GP0_CF[3:0]
Bit
7
6
5 and 4 -
•
•
275 MHz ≤ f
4 kHz ≤ f
Symbol
Symbol
I2CSW_EN
I2CSW_ON
GPIOREG_0 register (address 44h) bit description
GPIOREG_1 register (address 45h) bit description
i
Digital global standard low IF demodulator for analog TV and FM radio
/ N ≤ 150 MHz
All information provided in this document is subject to legal disclaimers.
VCO
≤ 550 MHz
Access Value
R/W
R/W
Access Value
R/W
R/W
R/W
Rev. 1 — 3 March 2011
0000
0001*
0011
0100
to
1011
XXXX
0000
0001
0011
0100
to
1011*
1*
0*
00*
Description
It determines how the general purpose pin GPIO1 is
configured.
It determines how the general purpose pin GPIO0 is
configured.
Description
When I2CSW_EN = 1, GPIO1 and GPIO2 are
configured as an I
the GP1_CF and GP2_CF value. When
I2CSW_ON = 0, the feed-through switch is open, and
GPIO1 and GPIO2 are in 3-state. When the switch is
closed (I2CSW_ON = 1), the I
signals (SCL and SDA) are available on the GPIO1 and
GPIO2 pins.
not used
The GPIO1 pin is in Input mode. The input value is
stored in GP1_VAL.
The GPIO1 pin is in Open-drain mode. The output
value is determined by GP1_VAL.
The GPIO1 pin is in Output mode. The PLL output
clock divided by two is delivered.
The GPIO1 pin is in Output mode. HVPLL signals are
delivered. The HVPLL signal is chosen according to
Table
Don’t care if I2CSW_EN = 1. Then the pad is
configured as I
Table
The GPIO0 pin is in Input mode. The input value is
stored in GP0_VAL.
The GPIO0 pin is in Open-drain mode. The output
value is determined by GP0_VAL.
The GPIO0 pin is in Output mode. The PLL output
clock divided by two is delivered.
The GPIO0 pin is in Output mode. HVPLL signals are
delivered. The HVPLL signal is chosen according to
Table
56.
55.
56.
2
C-bus feed-through like described in
2
C-bus feed-through independently of
2
C-bus clock and data
TDA8296
© NXP B.V. 2011. All rights reserved.
47 of 87