uda1352hl NXP Semiconductors, uda1352hl Datasheet - Page 13

• Manufacturer Part Number: uda1352hl
• Description: 48 Khz Iec 60958 Audio Dac
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.5
By default, the DAC outputs are muted until the
UDA1352HL is locked, regardless of the level on
pin MUTE or the state of bit MT. This allows only valid data
to be passed to the outputs. This mute is performed in the
SPDIF interface and is a hard mute, not a cosine roll-off
mute.
The UDA1352HL can be prevented from muting in
out-of-lock situations by setting bit MUTEBP in register
address 01H to logic 1 via the L3-bus or I
interfaces.
8.6
The UDA1352HL data path consists of the IEC 60958
decoder, audio feature processor, digital interpolator,
noise shaper and the DACs.
8.6.1
The IEC 60958 decoder features an on-chip amplifier with
hysteresis, which amplifies the SPDIF input signal to
CMOS level (see Fig.4).
All 24 bits of data for left and right channels are extracted
from the input bitstream plus 40 channel-status bits for left
and right channels. These bits can be read via the L3-bus
or I
2003 Mar 25
handbook, halfpage
48 kHz IEC 60958 audio DAC
2
Fig.4
C-bus interfaces.
75
Auto mute
Data path
IEC 60958
IEC 60958 input circuit and typical
application.
180 pF
10 nF
INPUT
SPDIF0,
SPDIF1
16,
17
UDA1352HL
2
C-bus
MGU611
13
The UDA1352HL supports the following sample
frequencies and data rates:
The UDA1352HL supports timing levels I, II and III, as
specified by the IEC 60958 standard. The accuracy of the
above sampling frequencies depends on the timing levels
used. Timing levels I, II and III are described in
Section 11.4.1.
8.6.2
The audio feature processor automatically provides
de-emphasis for the IEC 60958 data stream in the static
pin control mode and default mute at start-up in either the
L3-bus or I
When used in L3-bus or I
processor provides the following additional features:
f
f
f
Independent left and right channel volume control
Bass boost control
Treble control
Selection of sound processing modes for bass boost
and treble filters: flat, minimum and maximum
Soft mute control with raised cosine roll-off
De-emphasis of the incoming data stream selectable at
a sampling frequency of either 32.0, 44.1 or 48.0 kHz.
s
s
s
= 32.0 kHz, resulting in a data rate of 2.048 Mbits/s
= 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s
= 48.0 kHz, resulting in a data rate of 3.072 Mbits/s.
A
UDIO FEATURE PROCESSOR
2
C-bus mode.
2
C-bus modes, the audio feature
Preliminary specification
UDA1352HL