uda1360ts NXP Semiconductors, uda1360ts Datasheet - Page 4

• Manufacturer Part Number: uda1360ts
• Description: Low-voltage Low-power Stereo Audio Adc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
PINNING
FUNCTIONAL DESCRIPTION
System clock
The UDA1360TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable via the static FSEL pin, and the system clock
must be locked in frequency to the digital interface input
signals.
The options are 256f
(FSEL = HIGH). The sampling frequency range is
5 to 55 kHz.
The BCK clock can be up to 128f
BCK frequency is 128 times the Word Select (WS)
frequency or less: f
Notes:
1. The WS edge MUST fall on the negative edge of the
2. For MSB justified formats it is important to have a WS
2001 Mar 14
VINL
V
VINR
V
V
SFOR
PWON
SYSCLK
V
V
BCK
WS
DATAO
FSEL
V
V
SYMBOL
ref
ref(n)
ref(p)
DDD
SSD
SSA
DDA
Low-voltage low-power stereo audio ADC
BCK at all times for proper operation of the digital I/O
data interface.
signal with 50% duty factor.
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
BCK
s
(FSEL = LOW) and 384f
left channel input
reference voltage
right channel input
ADC negative reference voltage
ADC positive reference voltage
data format selection input
power control input
system clock input 256 or 384f
digital supply voltage
digital ground
bit clock input
word selection input
data output
system clock frequency select
analog ground
analog supply voltage
128
f
WS
DESCRIPTION
s
, or in other words the
.
s
s
4
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1360TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.
Input level
The overall system gain is proportional to V
input level is defined as that which gives a 1 dB FS digital
output (relative to the full-scale swing). In addition, an input
gain switch is incorporated with the above definitions.
The UDA1360TS front-end is equipped with a selectable
0 or 6 dB gain, in order to supports 2 V (RMS) input using
a series resistor of 12 k .
For the definition of the pin settings for 1 or 2 V (RMS)
mode given in Table 1, it is assumed that this resistor is
present as a default component.
If the 2 V (RMS) signal input is not needed, the external
resistor should not be used.
handbook, halfpage
SYSCLK
PWON
V ref(n)
V ref(p)
SFOR
VINR
VINL
V ref
Fig.2 Pin configuration.
1
2
3
4
5
6
7
8
UDA1360TS
MGM968
16
15
14
13
12
11
10
9
UDA1360TS
Product specification
V DDA
V SSA
FSEL
DATAO
WS
BCK
V SSD
V DDD
DDA
. The 0 dB