pca9542pw NXP Semiconductors, pca9542pw Datasheet - Page 4

• Manufacturer Part Number: pca9542pw
• Description: 2-channel I2c Multiplexer And Interrupt Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9542 is
shown in Figure 3. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9542 which will be stored
in the Control Register. If multiple bytes are received by the
PCA9542, it will save the last byte received. This register can be
written or read via the I
CONTROL REGISTER DEFINITION
A SCx/SDx downstream pair, or channel, is selected by the contents
of the control register. This register is written after the PCA9542 has
been addressed. The 3 LSBs of the control byte are used to
determine which channel is to be selected. When a channel is
selected, it will become active after a Stop condition has been
placed on the I
a HIGH state when the channel is made active, so that no false
conditions are generated at the time of connection.
Table 1. Control Register; Write — Channel Selection/
2004 Oct 01
Read — Channel Status
D7
X
X
X
X
0
2-channel I
D6
X
X
X
X
0
X
7
INT1
2
1
INTERRUPT BITS
C-bus. This ensures that all SCx/SDx lines will be in
X
X
X
X
0
(READ ONLY)
X
6
1
FIXED
INT1 INT0
Figure 4. Control register
INT0
Figure 3. Slave address
5
2
X
X
X
X
0
1
2
C-bus.
C multiplexer and interrupt logic
4
0
D3
X
X
X
X
0
ENABLE BIT
3
X
A2
HARDWARE SELECTABLE
B2
CHANNEL SELECTION BITS
2
B2
A1 A0
0
1
1
1
0
1
B1
(READ/WRITE)
B1
X
0
0
1
0
R/W
B0
0
B0
X
0
1
X
0
default state
COMMAND
No channel
No channel
No channel
Channel 0
Channel 1
power-up
selected;
selected
selected
enabled
enabled
SW00477
SW00862
4
POWER-ON RESET
When power is applied to V
the PCA9542 in a reset state until V
point, the reset condition is released and the PCA9542 registers and
I
causing all the channels to be deselected.
INTERRUPT HANDLING
The PCA9542 provides 2 interrupt inputs, one for each channel and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9542 and the interrupt output
will be driven LOW. The channel need not be active for detection of
the interrupt. A bit is also set in the control byte.
Bit 4 and Bit 5 of the control byte correspond to
channel 0 and channel 1 of the PCA9542, respectively. Therefore, if
an interrupt is generated by any device connected to channel 1, the
state of the interrupt inputs is loaded into the control register when a
read is accomplished. Likewise, an interrupt on any device connected
to channel 0 would cause bit 4 of the control register to be set on the
read. The master can then address the PCA9542 and read the
contents of the control byte to determine which channel contains the
device generating the interrupt. The master can then reconfigure the
PCA9542 to select this channel, and locate the device generating the
interrupt and clear it.
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
If unused, interrupt input(s) must be connected to V
pull-up resistor.
Table 2. Control Register; Read — Interrupt
NOTE: The 2 interrupts can be active at the same time.
2
C state machine are initialized to their default states, all zeroes
D7
0
0
0
0
D6
0
0
0
0
INT1
X
X
0
1
INT0
X
X
0
1
DD
D3
X
X
X
X
, an internal Power-On Reset holds
B2
DD
X
X
X
X
has reached V
B1
X
X
X
X
PCA9542
B0
X
X
X
X
Product data sheet
DD
POR
on channel 0
No interrupt
Interrupt on
channel 0
No interrupt
on channel 1
Interrupt on
channel 1
through a
COMMAND
. At this