pca9674a NXP Semiconductors, pca9674a Datasheet - Page 6

• Manufacturer Part Number: pca9674a
• Description: Remote 8-bit I/o Expander For Fm+ I2c-bus With Interrupt
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Functional description
Product data sheet
PCA9674_PCA9674A_2
7.1 Device address
Table 4.
[1]
Refer to
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9674/74A is shown in
64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in
Table 5 “PCA9674 address map”
Remark: When using the PCA9674A, the General Call address (0000 0000b) and the
Device ID address (1111 100Xb) are reserved and cannot be used as device address.
Failure to follow this requirement will cause the PCA9674A not to acknowledge.
Remark: When using the PCA9674 or the PCA9674A, reserved I
be used with caution since they can interfere with:
Symbol
AD2
P0
P1
P2
P3
V
P4
P5
P6
P7
INT
SCL
SDA
V
AD0
AD1
•
•
•
SS
DD
[1]
HVQFN package die supply ground is connected to both the V
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
“reserved for future use” I
1111 111)
slave devices that use the 10-bit addressing scheme (1111 0xx)
High speed mode (Hs-mode) master code (0000 1xx)
Figure 1 “Block diagram of
Pin description for HVQFN16
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Rev. 02 — 12 October 2006
Figure
Remote 8-bit I/O expander for Fm+ I
Description
address input 2
quasi-bidirectional I/O 0
quasi-bidirectional I/O 1
quasi-bidirectional I/O 2
quasi-bidirectional I/O 3
supply ground
quasi-bidirectional I/O 4
quasi-bidirectional I/O 5
quasi-bidirectional I/O 6
quasi-bidirectional I/O 7
interrupt output (active LOW)
serial clock line
serial data line
supply voltage
address input 0
address input 1
2
C-bus addresses (0000 011, 1111 101, 1111 110,
and
8. Slave address pins AD2, AD1, and AD0 choose 1 of
PCA9674/74A”.
Table 6 “PCA9674A address
SS
pin and the exposed center pad. The V
PCA9674/74A
2
C-bus addresses must
2
map”.
C-bus with interrupt
© NXP B.V. 2006. All rights reserved.
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SS