pca9673 NXP Semiconductors, pca9673 Datasheet
pca9673
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pca9673 Summary of contents
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... The difference between the PCA9673 and the PCF8575 is that the A2 address pin is replaced by a RESET input on the PCA9673. The device consists of a 16-bit quasi-bidirectional port and an I PCA9673 has a low current consumption and includes latched outputs with 25 mA high current drive capability for directly driving LEDs ...
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... Instrumentation and test measurement 4. Ordering information Table 1. Ordering information Type number Topside Package mark Name PCA9673D PCA9673D SO24 PCA9673DB PCA9673DB SSOP24 PCA9673DK PCA9673 SSOP24 PCA9673PW PCA9673PW TSSOP24 PCA9673BQ 9673 DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad PCA9673BS 9673 HVQFN24 [1] Also known as QSOP24 ...
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... Block diagram INT AD0 AD1 SCL SDA RESET Fig 1. Block diagram of PCA9673 data from Shift Register data to Shift Register Fig 2. Simplified schematic diagram of P00 to P17 PCA9673_1 Product data sheet Remote 16-bit I/O expander for Fm+ I PCA9673 INTERRUPT LOGIC 2 INPUT ...
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... P10 SS 002aac303 (QSOP24) Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset 1 INT AD1 2 RESET 3 4 P00 5 P01 P02 6 PCA9673PW P03 7 8 P04 P05 9 P06 10 11 P07 002aac302 Fig 4. Pin configuration for TSSOP24 INT 1 AD1 2 3 RESET ...
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... Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset terminal 1 index area AD1 2 3 RESET P00 4 P01 5 6 P02 PCA9673BQ 7 P03 P04 8 P05 9 10 P06 P07 11 Transparent top view Fig 8. Pin configuration for DHVQFN24 Description interrupt output (active LOW) address input 1 ...
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... AD0. Address values depending on AD1 and AD0 can be found in address Remark: The General Call address (0000 0000b) and the Device ID address (1111 100Xb) are reserved and cannot be used as device address. Failure to follow this requirement will cause the PCA9673 not to acknowledge. Remark: Reserved I with: • ...
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... V DD 7.2 Software Reset call, and Device ID addresses Two other different addresses can be sent to the PCA9673. • General Call address: allows to reset the PCA9673 through the I reception of the right I information. • Device ID address: allows to read ID information from the device (manufacturer, part identification, revision). See information ...
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... The PCA9673 acknowledges this value only. If the byte is not equal to 06h, the PCA9673 does not acknowledge it. If more than 1 byte of data is sent, the PCA9673 does not acknowledge any more. 5. Once the right byte has been sent and correctly acknowledged, the master sends a ...
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... STOP command. Remark: The reading of the Device ID can be stopped anytime by sending a NACK command. Remark: If the master continues to ACK the bytes after the third byte, the PCA9673 rolls back to the first byte and keeps sending the Device ID sequence until a NACK has been detected. ...
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... To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0 the Write mode is entered. The PCA9673 acknowledges and the master sends the first data byte for P07 to P00. After the PCA9673_1 ...
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... NXP Semiconductors first data byte is acknowledged by the PCA9673, the second data byte P17 to P10 is sent by the master. Once again, the PCA9673 acknowledges the receipt of the data. Each 8-bit data is presented on the port lines after it has been acknowledged by the PCA9673. The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is overwritten. The fi ...
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SCL P0x SDA DATA 00 START condition R/W acknowledge from slave read from port 0 data into port 0 DATA 00 ...
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SCL P0x SDA DATA 00 START condition R/W acknowledge from slave read from port 0 t h(D) data into port 0 ...
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... PCA9673 registers and I states. Thereafter V 8.5 Interrupt output (INT) The PCA9673 provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller (see chips a kind of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the port inputs. After time t signal INT is valid ...
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... Remote 16-bit I/O expander for Fm C-bus Figure SDA SCL data line stable; data valid Figure 21.) S START condition Figure 22). Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset 20). change of data allowed mba607 P STOP condition © NXP B.V. 2007. All rights reserved. SDA SCL mba608 ...
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... TRANSMITTER/ RECEIVER TRANSMITTER RECEIVER data output by transmitter data output by receiver SCL from master 1 S START condition 2 C-bus Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset MASTER MASTER TRANSMITTER/ MULTIPLEXER RECEIVER SLAVE not acknowledge acknowledge 2 8 clock pulse for acknowledgement 2 ...
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... AD0 AD1 V DD SDA SCL CORE INT PROCESSOR RESET AD0 AD1 Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset 24, P00 and P01 are inputs, and P02 V DD P00 temperature sensor P01 battery status P02 control for latch P03 control for switch ...
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... NXP Semiconductors 10.3 Differences between the PCA9673 and the PCF8575 The PCA9673 is a drop in replacement for the PCF8575 and can used without electrical or software modifications, but there is a difference in interrupt output release timing during the read operation. Write operations are identical. At the completion of each 8-bit write sequence the data is stored in its associated 8-bit write register at ACK or NACK. The fi ...
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... [1] - 1.8 0 150 0.5 1 0 PCA9673 Max Unit 5.5 V 500 2.0 V +0. 5 400 mA 300 +0 +0. 5 © ...
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... C to +85 C; unless otherwise specified. amb Conditions Standard mode 2 I C-bus Min 0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 [4][ and Figure 17 Figure 16 and Figure 17 100 Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset 2 Fast mode I C-bus Fast-mode Plus I Max Min Max Min 100 0 400 0 - 1.3 - 0.5 - 0.6 - 0.26 - 0.6 - 0.26 - 0 3.45 0.1 0.9 ...
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... LOW HIGH 1 /f SCL SU;DAT HD;DAT and Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset of the SCL signal) in order to IL STOP bit 0 acknowledge condition (R/W) (A) ( VD;DAT VD;ACK SU;STO 002aab175 ACK or read cycle t ...
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... 0.49 0.32 15.6 7.6 10.65 1.27 0.36 0.23 15.2 7.4 10.00 0.019 0.013 0.61 0.30 0.419 0.05 0.014 0.009 0.60 0.29 0.394 REFERENCES JEDEC JEITA MS-013 Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset detail 1.1 1.1 1.4 0.25 0.25 0.1 0.4 1.0 0.043 0.043 0.055 ...
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... MO-150 Rev. 01 — 1 February 2007 2 C-bus with interrupt and reset detail 7.9 1.03 0.9 1.25 0.2 0.13 7.6 0.63 0.7 EUROPEAN PROJECTION PCA9673 SOT340 ( 0.8 8 0.1 o 0.4 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2007. All rights reserved ...
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... Rev. 01 — 1 February 2007 2 C-bus with interrupt and reset detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION PCA9673 SOT355 ( 0.5 8 0.1 o 0.2 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2007. All rights reserved ...
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... 0.31 0.25 8.8 4.0 6.2 0.635 0.20 0.18 8.6 3.8 5.8 0.012 0.0098 0.344 0.157 0.244 0.025 0.008 0.0075 0.337 0.150 0.228 REFERENCES JEDEC JEITA MO-137 Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset detail ( 0.89 1.05 1 0.25 0.18 0.1 0.41 ...
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... 4.1 2.25 4.1 2.25 0.5 2.5 3.9 1.95 3.9 1.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 01 — 1 February 2007 2 C-bus with interrupt and reset detail 0.5 2.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION PCA9673 SOT616 ISSUE DATE 01-08-08 02-10-22 © NXP B.V. 2007. All rights reserved ...
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... 2.5 scale (1) ( 5.6 4.25 3.6 2.25 0.5 4.5 5.4 3.95 3.4 1.95 REFERENCES JEDEC JEITA - - - - - - Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset detail 0.5 1.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION ...
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... Inspection and repair • Lead-free soldering versus PbSn soldering 16.3 Wave soldering Key characteristics in wave soldering are: PCA9673_1 Product data sheet Remote 16-bit I/O expander for Fm+ I Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 34. Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset Figure 34) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
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... Light Emitting Diode Least Significant Bit Machine Model Most Significant Bit Programmable Logic Controller Redundant Array of Independent Disks System Management Bus Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset peak temperature time 001aac844 © NXP B.V. 2007. All rights reserved. ...
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... Revision history Document ID Release date PCA9673_1 20070201 PCA9673_1 Product data sheet Remote 16-bit I/O expander for Fm+ I Data sheet status Product data sheet Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset Change notice Supersedes - - © NXP B.V. 2007. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 1 February 2007 PCA9673 2 C-bus with interrupt and reset © NXP B.V. 2007. All rights reserved ...
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... Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 Address maps 7.2 Software Reset call, and Device ID addresses. 7 7.2.1 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2.2 Device ID (PCA9673 ID field I/O programming . . . . . . . . . . . . . . . . . . . . . . . 10 8.1 Quasi-bidirectional I/O architecture . . . . . . . . 10 8.2 Writing to the port (Output mode 8.3 Reading from a port (Input mode 8.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 14 8.5 Interrupt output (INT 8.6 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ...