tda9981bhl NXP Semiconductors, tda9981bhl Datasheet
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tda9981bhl Summary of contents
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... Rev. 01 — 4 July 2008 1. General description The TDA9981B is an HDMI transmitter (which also supports DVI) that enables a 3 RGB or YCbCr video stream (with a pixel rate up to 150 MHz for the TDA9981BHL/15 version the additional information required by all the HDMI 1.2a standards. ...
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... V DDC(1V8) T amb TDA9981BHL/ MHz f clk(max) P cons P tot P pd TDA9981BHL/15 150 MHz f clk(max) P cons P tot P pd [1] Worst case: video input format: 720p (RGB embedded sync), video output format: 720p (YCbCr 4). [2] Video input format: 1080p (RGB embedded sync, rising edge), video output format: 1080p (RGB ...
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... NXP Semiconductors 5. Ordering information Table 2. Type number TDA9981BHL 5.1 Ordering options Table 3. Extended type number TDA9981BHL/8/C1xx TDA9981BHL/15/C1xx TDA9981B_1 Product data sheet Ordering information Package Name Description LQFP80 plastic low profile quad flat package; 80 leads; body 12 12 Survey of type numbers ...
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RST_N 42 18 HPD HARD HPD MANAGEMENT RESET AP7 to AP0 AUDIO 12 PROCESSING ACLK DATA ISLAND PACKET INFORMATION FRAMES AND PACKETS VPA[7:0] 57 and 58 65, 67 VPB[7:0] ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning HSYNC/HREF 1 2 VSYNC/VREF AP7 4 5 AP6 AP5 6 AP4 7 AP3 8 9 AP2 AP1 10 AP0 11 12 ACLK 13 V DDD(3V3 SSD V 15 SSC 16 V DDC(1V8) INT 17 HPD 18 19 DDC_SDA 20 DDC_SCL Fig 2. Pin configuration 7.2 Pin description Table 4. ...
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... NXP Semiconductors Table 4. Symbol AP4 AP3 AP2 AP1 AP0 ACLK V DDD(3V3) V SSD V SSC V DDC(1V8) INT HPD DDC_SDA DDC_SCL TM V SSA(FRO_3V3) V DDA(FRO_3V3) EXT_SWING V SSH TXC TXC+ V DDH(3V3) TX0 TX0+ V SSH TX1 TX1+ V DDH(3V3) TX2 TX2+ V SSH V DDA(PLL_3V3) V SSA(PLL_3V3 RST_N TDA9981B_1 Product data sheet Pin description … ...
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... NXP Semiconductors Table 4. Symbol I2C_SCL I2C_SDA V DDC(1V8) V SSA(PLL_1V8) V SSD V DDD(3V3) VPC[7] VPC[6] VPC[5] VPC[4] VPC[3] VPC[2] VPC[1] VPC[0] VPB[7] VPB[6] V DDC(1V8) V SSC VPB[5] VPB[4] VPB[3] VPB[2] VPB[1] VCLK VPB[0] VPA[7] VPA[6] VPA[5] V DDD(3V3) V SSD V SSC V DDC(1V8) VPA[4] VPA[3] VPA[2] VPA[1] VPA[0] ...
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... NXP Semiconductors 8. Functional description The TDA9981B is designed to convert digital data (video and audio) into an HDMI or a DVI stream. This HDMI stream can handle RGB, YCbCr and YCbCr The TDA9981B can accept at its inputs any of the following video modes: • ...
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Table 5. Inputs of video input formatter Color Format Channels Sync space RGB 8-bit external external embedded embedded YCbCr 8-bit external external embedded embedded YCbCr ...
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... NXP Semiconductors Table 6. RGB mappings RGB 8-bit) external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Video port B Pin RGB Pin VPA[0] B[0] VPB[0] VPA[1] B[1] VPB[1] VPA[2] B[2] VPB[2] VPA[3] B[3] VPB[3] VPA[4] B[4] VPB[4] VPA[5] B[5] VPB[5] ...
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... NXP Semiconductors Table 7. YCbCr mappings YCbCr 8-bit) external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Video port B Pin YCbCr Pin VPA[0] CB[0] VPB[0] VPA[1] CB[1] VPB[1] VPA[2] CB[2] VPB[2] VPA[3] CB[3] VPB[3] VPA[4] CB[4] VPB[4] VPA[5] CB[5] VPB[5] ...
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... NXP Semiconductors Table 8. YCbCr ITU656-like external synchronization single edge mappings YCbCr : ITU656-like external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr (ITU656-like) VPA[0] CB[0] Y0[0] CR[0] VPA[1] CB[1] Y0[1] CR[1] VPA[2] CB[2] Y0[2] CR[2] VPA[3] CB[3] Y0[3] CR[3] VPA[ VPA[ VPA[ VPA[ VCLK HSYNC/HREF ...
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... NXP Semiconductors Table 9. YCbCr ITU656-like external synchronization double edge mappings YCbCr ITU656-like external synchronization double edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr (ITU656-like) VPA[0] CB[0] Y0[0] CR[0] VPA[1] CB[1] Y0[1] CR[1] VPA[2] CB[2] Y0[2] CR[2] VPA[3] CB[3] Y0[3] CR[3] VPA[ VPA[ VPA[ VPA[ VCLK HSYNC/HREF ...
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... NXP Semiconductors Table 10. YCbCr ITU656-like embedded synchronization single edge mappings YCbCr ITU656-like embedded synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr (ITU656-like) VPA[0] CB[0] Y0[0] CR[0] VPA[1] CB[1] Y0[1] CR[1] VPA[2] CB[2] Y0[2] CR[2] VPA[3] CB[3] Y0[3] CR[3] VPA[ VPA[ VPA[ VPA[ VCLK VPB[7:0]; VPA[3:0] Cb0 Fig 7 ...
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... NXP Semiconductors Table 11. YCbCr ITU656-like embedded synchronization double edge mappings YCbCr ITU656-like embedded synchronization double edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr (ITU656-like) VPA[0] CB[0] Y0[0] CR[0] VPA[1] CB[1] Y0[1] CR[1] VPA[2] CB[2] Y0[2] CR[2] VPA[3] CB[3] Y0[3] CR[3] VPA[ VPA[ VPA[ VPA[ VCLK VPB[7:0]; VPA[3:0] Cb0 Fig 8 ...
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... NXP Semiconductors Table 12. YCbCr semi-planar external synchronization mappings YCbCr semi-planar external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Video port B Pin YCbCr Pin semi-planar VPA[0] Y0[0] Y1[0] VPB[0] VPA[1] Y0[1] Y1[1] VPB[1] VPA[2] Y0[2] Y1[2] VPB[2] VPA[3] Y0[3] Y1[3] VPB[3] VPA[4] ...
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... NXP Semiconductors Table 13. YCbCr semi-planar embedded synchronization mappings YCbCr semi-planar embedded synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Video port B Pin YCbCr Pin semi-planar VPA[0] Y0[0] Y1[0] VPB[0] VPA[1] Y0[1] Y1[1] VPB[1] VPA[2] Y0[2] Y1[2] VPB[2] VPA[3] Y0[3] Y1[3] VPB[3] VPA[4] ...
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... NXP Semiconductors 8.3 Synchronization The TDA9981B can be synchronized with Hsync/Vsync external inputs or with extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream. 8.3.1 Timing extraction generator This block can extract the synchronization signals Href, Vref and Fref from Start Active Video (SAV) and End Active Video (EAV) in case of embedded synchronization in the data stream ...
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... NXP Semiconductors 8.6 Color space converter The color space converter is used to convert input video data from one type to another color space (RGB to YCbCr and YCbCr to RGB). This block can be bypassed and each coefficient is programmable via the 8.7 Downsampler This block works only with YCbCr input format ...
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... NXP Semiconductors serial clock. Various I appropriate bits of the register. The I audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency f precision can be received automatically. Audio samples with a precision better than 24 bits are truncated to 24 bits. If the input clock has a frequency of 32 samples can be received ...
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... NXP Semiconductors 8.14 HDMI 8.14.1 Output HDMI buffers An external resistor must be used to set the HDMI output amplitude. It has to be connected between pin EXT_SWING and V 8.14.2 Pixel repetition To transmit video formats with pixel rates below 25 MHz or to increase the number of audio sample packets in each frame, the TDA9981B uses pixel repetition to increase the transmitted pixel clock ...
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... NXP Semiconductors Fig 12. Receiver sensitivity detection As long as the receiver is connected to the transmitter and powered up, bit RXS_FIL is set to logic 1. When the cable is unplugged or the receiver site is powered off (assuming in this case that V DD changing the value of bit RXS_FIL to logic 0. This allows the application to stop sending unnecessary video content ...
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... NXP Semiconductors For read access, the master writes the address of the TDA9981B, the subaddress to access the specific register and then the data. Fig 13. I 10. Limiting values Table 18. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DD(3V3) V DD(1V8) ...
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... V) DDC(1V8) f maximum clock frequency clk(max) P power consumption cons P total power dissipation tot P power dissipation in Power-down mode pd TDA9981BHL/15 150 MHz I free running oscillator 3.3 V analog supply current DDA(FRO_3V3) I PLL 3.3 V analog supply current DDA(PLL_3V3) I digital supply current (3.3 V) DDD(3V3) I HDMI supply current (3.3 V) DDH(3V3) I core supply current (1 ...
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... NXP Semiconductors Table 21. LV-TTL digital inputs and outputs DDA(FRO_3V3) DDA(PLL_3V3 1. 1. DDC(1V8) PP Typical values are measured at V and unless otherwise specified. amb Symbol Parameter Not 5 V tolerant inputs: pins HSYNC, VSYNC, AP[7:0], ACLK, TM, A0, A1, VPA[7:0], VPB[7:0], VPC[7:0], VCLK, DE ...
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... amb = DDA(FRO_3V3) DDA(PLL_3V3) DDH(3V3) Conditions TDA9981BHL/8 TDA9981BHL/15 standard mode standard mode fast mode TDA9981BHL/8 TDA9981BHL/15 TDA9981BHL/8 TDA9981BHL/15 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter = 3.6 V; DDD(3V3 3 DDD(3V3) DDC(1V8) Min Typ Figure ...
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... NXP Semiconductors 13.1 Input format In Table 24 been mapped to Y (YUV space)/G (RGB space) and VPC has been mapped to CR (YUV space)/R (RGB space). Table 24. Input format Input pins Signal RGB Video port A VPA[0] CB[0]/B[0] B[0] VPA[1] CB[1]/B[1] B[1] VPA[2] CB[2]/B[2] B[2] VPA[3] CB[3]/B[3] B[3] VPA[4] CB[4]/B[4] B[4] VPA[5] CB[5]/B[5] B[5] VPA[6] CB[6]/B[6] B[6] VPA[7] CB[7]/B[7] B[7] Video port B ...
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... NXP Semiconductors 13.2 Example of supported video The TDA9981B supports all EIA/CEA-861B, ATSC video input formats. Table 25. Timing parameters for EIA/CEA-861B Format nr. Format 59.94 Hz systems 1 (VGA) 640 480p 2, 3 720 480p 4 1280 720p 5 1920 1080i 6, 7 (NTSC) 720 480i 8, 9 720 240p 8, 9 720 ...
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... Various systems 32 1920 1080p 32 1920 1080p 33 1920 1080p 34 1920 1080p 34 1920 1080p [1] Only for TDA9981BHL/15. Table 26. Timing parameters for PC standards below 150 MHz Standard Format 640 350p 640 400p 720 400p 0.31M3 640 480p VGA 640 480p 640 480p ...
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... Only for TDA9981BHL/15. TDA9981B_1 Product data sheet …continued V frequency H total V total (Hz) 119.989 1184 813 75.000 1600 900 59.995 1440 790 119.798 1440 813 59.870 1664 798 74 ...
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... NXP Semiconductors 13.3 Timing diagrams VCLK t clk(H) HSYNC/HREF CONTROL VSYNC/VREF INPUTS DE/FREF VPA[7:0] B0 VPB[7:0] G0 VPC[7: h(D) t su(D) Fig 14. Timing RGB (rising edge) input VCLK t clk(H) HSYNC/HREF CONTROL VSYNC/VREF INPUTS DE/FREF VPA[7:0] Cb0 VPB[7:0] Y0 Cr0 VPC[7:0] t h(D) t su(D) Fig 15. Timing YCbCr (rising edge) input ...
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... NXP Semiconductors VCLK t clk(H) HSYNC/HREF CONTROL VSYNC/VREF INPUTS DE/FREF VPB[7:0]; VPA[3:0] Cb0 t h(D) t su(D) Fig 17. Timing YCbCr ITU656-like single edge external (rising edge) input VCLK t clk(H) HSYNC/HREF CONTROL VSYNC/VREF INPUTS DE/FREF VPB[7:0]; VPA[3:0] Y0 VPC[7:0]; VPA[7:4] Cb0 Fig 18. Timing YCbCr semi-planar external synchronization (rising edge) input ...
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... NXP Semiconductors 14. Application information LO Fig 19. Application diagram for Set-Top Box DVD READ ENGINE Fig 20. Application diagram for DVD player TDA9981B_1 Product data sheet G ADC DSP audio AUX 2 I S-bus data or S/PDIF DENC DSP audio AUX 2 I S-bus data or S/PDIF AUDIO DAC Rev. 01 — ...
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... NXP Semiconductors MICROPROCESSOR MASTER audio, S/PDIF and I MPEG2 DECODER MASTER HDMI SOURCE Fig 21. Transmitter connection with external world TDA9981B_1 Product data sheet reset digital video ( bits) sync signals HDMI TDA9981B 2 S-bus IRQ C-bus I C-bus SLAVE MASTER Rev. 01 — 4 July 2008 ...
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... NXP Semiconductors 15. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.16 1.5 1.6 mm 0.25 0.04 1.3 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Soldering: additional information The package of this device supports the reflow soldering process only. 18. Abbreviations Table 29 ...
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... NXP Semiconductors Table 29. Acronym HDTV HPD IRQ LO L-PCM LSB LV-TTL MSB OTP PAL PCM PLL PVR RGB SAV STB S/PDIF TMDS Tx XGA YUV YCbCr 19. Revision history Table 30. Revision history Document ID Release date TDA9981B_1 20080704 TDA9981B_1 Product data sheet Abbreviations …continued Description High-Defi ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 8 8.1 System clock 8.2 Video input processor . . . . . . . . . . . . . . . . . . . . 8 8.3 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 18 8.3.1 Timing extraction generator . . . . . . . . . . . . . . 18 8.3.2 Data enable generator . . . . . . . . . . . . . . . . . . 18 8 ...