tda9983bhw/8/c1 NXP Semiconductors, tda9983bhw/8/c1 Datasheet
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tda9983bhw/8/c1 Summary of contents
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TDA9983B HDMI transmitter up to 150 MHz pixel rate with 3 inputs and 4 Rev. 01 — 20 May 2008 1. General description The TDA9983B is an HDMI transmitter (which also supports DVI) that enables a 3 RGB or YC ...
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... NXP Semiconductors I Hard reset 3. Applications I DVD players and recorders I Set-Top Box (STB receivers and amplifiers (repeater) I Camcorders I Digital still cameras I Media players I PVRs I Media centers PCs, graphics add-in boards, notebook PCs I Switches 4. Quick reference data Table 1. V DDA(FRO_3V3) V DDD(3V3) ...
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... Input 1080p (RGB external sync, rising edge) b) Output 1080p (RGB Ordering information Table 2. Type number TDA9983BHW 5.1 Ordering options Table 3. Extended type number TDA9983BHW/8/C1 TDA9983BHW/15/C1 TDA9983B_1 Product data sheet Quick reference data …continued = 3 3 DDA(PLL_3V3 ...
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RST_N 42 HPD 18 HARD HPD MANAGEMENT RESET AP7 to AP0 AUDIO 12 PROCESSING ACLK DATA ISLAND PACKET INFORMATION FRAMES AND PACKETS VPA[7:0] 57 and 58 65, 67 VPB[7:0] ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning HSYNC/HREF 1 VSYNC/VREF AP7 AP6 5 AP5 6 7 AP4 AP3 8 AP2 9 AP1 10 11 AP0 ACLK DDD(3V3 SSD 15 V SSC V 16 DDC(1V8) INT 17 18 HPD DDC_SDA 19 DDC_SCL 20 Fig 2. Pin configuration 7.2 Pin description Table 4. Symbol ...
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... NXP Semiconductors Table 4. Symbol AP4 AP3 AP2 AP1 AP0 ACLK V DDD(3V3) V SSD V SSC V DDC(1V8) INT HPD DDC_SDA DDC_SCL TM V SSA(FRO_3V3) V DDA(FRO_3V3) EXT_SWING V SSH TXC TXC+ V DDH(3V3) TX0 TX0+ V SSH TX1 TX1+ V DDH(3V3) TX2 TX2+ V SSH V DDA(PLL_3V3) V SSA(PLL_3V3 RST_N TDA9983B_1 Product data sheet Pin description … ...
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... NXP Semiconductors Table 4. Symbol I2C_SCL I2C_SDA V DDC(1V8) V SSA(PLL_1V8) V SSD V DDD(3V3) VPC[7] VPC[6] VPC[5] VPC[4] VPC[3] VPC[2] VPC[1] VPC[0] VPB[7] VPB[6] V DDC(1V8) V SSC VPB[5] VPB[4] VPB[3] VPB[2] VPB[1] VCLK VPB[0] VPA[7] VPA[6] VPA[5] V DDD(3V3) V SSD V SSC V DDC(1V8) VPA[4] VPA[3] VPA[2] VPA[1] VPA[0] ...
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... NXP Semiconductors [ power supply ground input output. 8. Functional description The TDA9983B is designed to convert digital data (video and audio) into an HDMI or a DVI stream. This HDMI stream can handle RGB, YC TDA9983B can accept at its inputs any of the following video modes: • ...
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Table 5. Inputs of video input formatter Color Format Channels Sync space RGB 8-bit external external embedded embedded 8-bit external B R external embedded embedded YC ...
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... NXP Semiconductors Table 6. RGB mappings RGB 8-bit) external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Video port B Pin RGB Pin VPA[0] B[0] VPB[0] VPA[1] B[1] VPB[1] VPA[2] B[2] VPB[2] VPA[3] B[3] VPB[3] VPA[4] B[4] VPB[4] VPA[5] B[5] VPB[5] ...
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... NXP Semiconductors Table mappings 8-bit) external synchronization single edge Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Video port B Pin Pin B R VPA[0] C [0] VPB[0] B VPA[1] C [1] VPB[1] B VPA[2] C [2] ...
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... NXP Semiconductors Table ITU656-like external synchronization single edge mappings ITU656-like external synchronization single edge Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin (ITU656-like VPA[0] C [0] Y [ VPA[1] C ...
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... NXP Semiconductors Table ITU656-like external synchronization double edge mappings ITU656-like external synchronization double edge Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin (ITU656-like VPA[0] C [0] Y [ VPA[1] C ...
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... NXP Semiconductors Table 10 ITU656-like embedded synchronization single edge mappings ITU656-like embedded synchronization single edge Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin (ITU656-like VPA[0] C [0] Y [ VPA[1] C ...
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... NXP Semiconductors Table 11 ITU656-like embedded synchronization double edge mappings ITU656-like embedded synchronization double edge Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin (ITU656-like VPA[0] C [0] Y [ VPA[1] C ...
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... NXP Semiconductors Table 12 semi-planar external synchronization mappings semi-planar external synchronization single edge Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Video port B Pin Pin B R semi-planar VPA[0] Y [0] Y [0] VPB[ VPA[1] ...
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... NXP Semiconductors Table 13 semi-planar embedded synchronization mappings semi-planar embedded synchronization single edge Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Video port B Pin Pin B R semi-planar VPA[0] Y [0] Y [0] VPB[ VPA[1] ...
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... NXP Semiconductors 8.3 Synchronization The TDA9983B can be synchronized with Hsync/Vsync external inputs or with extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream. 8.3.1 Timing extraction generator This block can extract the synchronization signals Href, Vref and Fref from Start Active Video (SAV) and End Active Video (EAV) in case of embedded synchronization in the data stream ...
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... NXP Semiconductors 8.6 Color space converter The color space converter is used to convert input video data from one type to another color space (RGB to YC coefficient is programmable via the 8.7 Downsampler This block works only with YC signals by a factor 2. A delay is added on the G/Y channel, which corresponds to the pipeline delay of the fi ...
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... NXP Semiconductors serial clock. Various I appropriate bits of the register. The I audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency f precision can be received automatically. Audio samples with a precision better than 24 bits are truncated to 24 bits. If the input clock has a frequency of 32 samples can be received ...
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... NXP Semiconductors 8.14 HDMI 8.14.1 Output HDMI buffers An external resistor must be used to set the HDMI output amplitude. It has to be connected between pin EXT_SWING and V 8.14.2 Pixel repetition To transmit video formats with pixel rates below 25 Msample increase the number of audio sample packets in each frame, the TDA9983B uses pixel repetition to increase the transmitted pixel clock ...
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... NXP Semiconductors • Embedded deinterlacer (no need for output memory) • Maximum output operating frequency: 74.5 MHz (HDTV supported 1080i, 720p) • Input video standards (YC no RGB and no YC 8.16 Input and output video scaler The scaler converts the standard definition video signals (480i/576i, 480p/576p) into ...
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... NXP Semiconductors C-bus register definitions 2 9.1 I C-bus protocol The registers of the TDA9983B can be accessed via the slave device and both the fast mode 400 kHz and the standard mode 100 kHz are supported. Bits A0 and A1 of the I 2 The I C-bus device address is given in Table 17 ...
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Table 19. I C-bus registers of memory page 00h Register Sub R/W addr 7 (MSB) VERSION 00h R 0 MAIN_CNTRL0 01h W SCALER Not used 02h - : : : Not used 0Eh - INT_FLAGS_0 0Fh R/W x INT_FLAGS_1 ...
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Table 19. I C-bus registers of memory page 00h Register Sub R/W addr 7 (MSB) MAT_P21_MSB 8Dh W x MAT_P21_LSB 8Eh W MAT_P22_MSB 8Fh W x MAT_P22_LSB 90h W MAT_P23_MSB 91h W x MAT_P23_LSB 92h W MAT_P31_MSB 93h W ...
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Table 19. I C-bus registers of memory page 00h Register Sub R/W addr 7 (MSB) VS_LINE_END_1_MSB ADh W x VS_LINE_END_1_LSB AEh W VS_PIX_END_1_MSB AFh W x VS_PIX_END_1_LSB B0h W VS_LINE_STRT_2_MSB B1h W x VS_LINE_STRT_2_LSB B2h W VS_PIX_STRT_2_MSB B3h W ...
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Table 19. I C-bus registers of memory page 00h Register Sub R/W addr 7 (MSB) VBL_OFFSET_START CCh W VBL_OFFSET_END CDh W HBL_OFFSET_START CEh W HBL_OFFSET_END CFh W DWIN_RE_DE D0h W DWIN_FE_DE D1h W Not used D2h - : : ...
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Table 19. I C-bus registers of memory page 00h Register Sub R/W addr 7 (MSB) Not used FCh - - AIP_CLKSEL FDh W x GHOST_ADDR FEh W CURPAGE_ADR FFh W [1] R: reading register W: writing register x: bit ...
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... NXP Semiconductors 9.3.1 Main control register Table 20. Legend default value Bit Table 21. Legend default value Bit 9.3.2 Interrupt flags/masks registers Table 22. Legend default value Bit TDA9983B_1 Product data sheet VERSION register (address 00h) bit description ...
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... NXP Semiconductors Table 23. Legend default value Bit 9.3.3 Video input processing control registers Table 24. Legend default value Bit TDA9983B_1 Product data sheet INT_FLAGS_1 register (address 10h) bit description Symbol Access Value HPD_IN R R/W 0* SC_DEIL R SC_VID ...
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... NXP Semiconductors Table 24. Legend default value Bit Table 25. Legend default value Bit Table 26. Legend default value Bit 7 TDA9983B_1 Product data sheet VIP_CNTRL_0 register (address 20h) bit description Symbol Access Value SWAP_B[2:0] W 000 001* 010 011 100 ...
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... NXP Semiconductors Table 26. Legend default value Bit Table 27. Legend default value Bit TDA9983B_1 Product data sheet VIP_CNTRL_2 register (address 22h) bit description Symbol Access Value SWAP_E[2:0] W 000 001 010 011 100 101* other MIRR_F W 0* ...
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... NXP Semiconductors Table 27. Legend default value Bit 1 0 Table 28. Legend default value Bit Table 29. Legend default value Bit TDA9983B_1 Product data sheet VIP_CNTRL_3 register (address 23h) bit description Symbol Access Value H_TGL ...
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... NXP Semiconductors Table 29. Legend default value Bit 0 9.3.4 Color space conversion registers Table 30. Legend default value Bit and 0 Table 31. Offset input registers (address 81h to 86h) bit description Legend default value Address Register Bit 81h MAT_OI1_MSB OFFSET_IN1[10:8] 82h ...
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... NXP Semiconductors Table 32. Coefficient registers (address 87h to 98h) bit description Legend default value Address Register Bit 87h MAT_P11_MSB P11[10:8] 88h MAT_P11_LSB P11[7:0] 89h MAT_P12_MSB P12[10:8] 8Ah MAT_P12_LSB P12[7:0] 8Bh MAT_P13_MSB P13[10:8] ...
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... NXP Semiconductors Table 33. Offset output registers (address 99h to 9Eh) bit description Legend default value Address Register Bit 9Dh MAT_OO3_MSB OFFSET_OUT3[10:8] W 9Eh MAT_OO3_LSB OFFSET_OUT3[7:0] [1] The value is a signed 11-bit two’s complement integer. 9.3.5 Video format registers Table 34. ...
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... NXP Semiconductors Table 36. VS_LINE_STRT_xx, VS_PIX_STRT_xx, VS_LINE_END_xx, VS_PIX_END_xx registers (address A9h to B8h) bit description Legend default value Address Register A9h VS_LINE_STRT_1_MSB AAh VS_LINE_STRT_1_LSB VS_LINE_START_1[7:0] ABh VS_PIX_STRT_1_MSB ACh VS_PIX_STRT_1_LSB ADh VS_LINE_END_1_MSB AEh VS_LINE_END_1_LSB AFh VS_PIX_END_1_MSB B0h VS_PIX_END_1_LSB B1h VS_LINE_STRT_2_MSB ...
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... NXP Semiconductors Table 37. HS_PIX_xx registers (address B9h to BCh) bit description Legend default value Address Register B9h HS_PIX_START_MSB BAh HS_PIX_START_LSB BBh HS_PIX_STOP_MSB BCh HS_PIX_STOP_LSB Table 38. VWIN_START_xx and VWIN_END_xx registers (address BDh and C4h) bit description Legend default value Address Register BDh VWIN_START_1_MSB ...
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... NXP Semiconductors Table 41. Legend default value Bit Table 42. Legend default value Bit TDA9983B_1 Product data sheet TBG_CNTRL_0 register (address CAh) bit description Symbol Access Value SYNC_ONCE SYNC_MTHD FRAME_DIS 0000* ...
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... NXP Semiconductors Table 43. OFFSET registers (address CCh to CFh) bit description Legend default value Address Register CCh VBL_OFFSET_START CDh VBL_OFFSET_END CEh HBL_OFFSET_START CFh HBL_OFFSET_END Table 44. DWIN_xx_DE registers (address D0h and D1h) bit description Legend default value Address Register D0h DWIN_RE_DE D1h DWIN_FE_DE 9 ...
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... NXP Semiconductors Table 45. Legend default value Bit Table 46. Legend default value Bit TDA9983B_1 Product data sheet HVF_CNTRL_0 register (address E4h) bit description Symbol Access Value INTPOL[1: HVF_CNTRL_1 register (address E5h) bit description Symbol ...
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... NXP Semiconductors 9.3.7 Timer control registers Table 47. Timer control registers (address E8h to EAh) bit description Legend default value Address Register Bit E8h TIMER_H E9h TIMER_M EAh TIMER_L 9.3.8 NDIV register Table 48. NDIV_xxx registers (address EEh and EFh) bit description ...
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... NXP Semiconductors Table 49. Control registers (address F0h to F2h, F9h, FDh and FEh) bit description Legend default value Address Register Bit F2h TRAIL_OFF F9h GHOST_XADDR FDh AIP_CLKSEL FEh GHOST_ADDR 9.3.10 Current page address register Table 50 ...
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Table 51. I C-bus registers of memory page 01h Register Sub R/W addr 7 (MSB) SC_VIDFORMAT 00h W LUT_SEL[1:0] SC_CNTRL 01h W x SC_DELTA_PHASE_V 02h W x SC_DELTA_PHASE_H 03h W x SC_START_PHASE_H 04h W x SC_NPIX_IN_LSB 05h W SC_NPIX_IN_MSB ...
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Table 51. I C-bus registers of memory page 01h Register Sub R/W addr 7 (MSB) SC_VS_LUT_4 1Fh W SC_VS_LUT_5 20h W SC_VS_LUT_6 21h W SC_VS_LUT_7 22h W SC_VS_LUT_8 23h W SC_VS_LUT_9 24h W SC_VS_LUT_10 25h W SC_VS_LUT_11 26h W ...
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Table 51. I C-bus registers of memory page 01h Register Sub R/W addr 7 (MSB) SC_VS_LUT_36 3Fh W SC_VS_LUT_37 40h W SC_VS_LUT_38 41h W SC_VS_LUT_39 42h W SC_VS_LUT_40 43h W SC_VS_LUT_41 44h W SC_VS_LUT_42 45h W SC_VS_LUT_43 46h W ...
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Table 51. I C-bus registers of memory page 01h Register Sub R/W addr 7 (MSB) DE_START_MSB C5h W x DE_START_LSB C6h W DE_STOP_MSB C7h W x DE_STOP_LSB C8h W Not used C9h - - TBG_CNTRL_0 CAh W SYNC_ ONCE ...
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... NXP Semiconductors 9.4.1 Scaler control registers Table 52. Legend default value Bit 7 and 6 LUT_SEL[1: Table 53. Legend default value Bit TDA9983B_1 Product data sheet SC_VIDFORMAT register (address 00h) bit description Symbol Access Value Description W 00 VID_FORMAT_O[2:0] W 000* ...
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... NXP Semiconductors Table 54. SC_x_PHASE_x registers (address 02h to 04h) bit description Legend default value Address Register 02h SC_DELTA_PHASE_V 03h SC_DELTA_PHASE_H 04h SC_START_PHASE_H Table 55. SC_NPIX_xx registers (address 05h to 08h) bit description Legend default value Address Register 06h SC_NPIX_IN_MSB 05h SC_NPIX_IN_LSB 08h SC_NPIX_OUT_MSB 07h SC_NPIX_OUT_LSB Table 56 ...
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... NXP Semiconductors Table 57. SC_x_BUFFILL_xx registers (address 0Eh to 12h) bit description Legend default value Address Register 12h SC_MAX_BUFFILL_D_1 11h SC_MAX_BUFFILL_D_0 Table 58. SC_xx_FIFOFILL_xx registers (address 13h to 1Ah) bit description Legend default value Address Register 13h SC_SAMPLE_FIFOFILL 14h SC_MAX_FIFOFILL_PI 15h SC_MIN_FIFOFILL_PO1 16h ...
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... NXP Semiconductors Table 59. SC_VS_LUT_xx registers (address 1Bh to 47h) bit description Legend default value Address Register Bit 1Bh SC_VS_LUT_0 1Ch SC_VS_LUT_1 1Dh SC_VS_LUT_2 1Eh SC_VS_LUT_3 1Fh SC_VS_LUT_4 20h SC_VS_LUT_5 21h SC_VS_LUT_6 22h SC_VS_LUT_7 23h ...
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... NXP Semiconductors Table 59. SC_VS_LUT_xx registers (address 1Bh to 47h) bit description Legend default value Address Register Bit 32h SC_VS_LUT_23 33h SC_VS_LUT_24 34h SC_VS_LUT_25 35h SC_VS_LUT_26 36h SC_VS_LUT_27 37h SC_VS_LUT_28 38h SC_VS_LUT_29 39h SC_VS_LUT_30 3Ah ...
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... NXP Semiconductors 9.4.2 Scaling input time base generator control registers Table 60. Legend default value Bit Table 61. REFPIX_xx, REFLINE_xx, NPIX_xx and NLINE_xx registers (address A1h to A8h) bit description Legend default value Address Register A1h REFPIX_MSB A2h REFPIX_LSB A3h REFLINE_MSB A4h ...
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... NXP Semiconductors Table 62. VWIN_START_x_xx and VWIN_END_x_xx registers (address BDh to C4h) bit description Legend default value Address Register C3h VWIN_END_2_MSB C4h VWIN_END_2_LSB Table 63. DE_START_x and DE_STOP_x registers (address C5h to C8h) bit description Legend default value Address Register C5h DE_START_MSB C6h DE_START_LSB C7h ...
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... NXP Semiconductors Table 64. Legend default value Bit 1 0 9.4.3 Current page address register Table 65. Legend default value Bit 9.5 PLL settings page register definitions The current page address for the PLL settings page is 02h. The configuration of the registers for this page is given in ...
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Table 66. I C-bus registers of memory page 02h Register Sub R/W addr 7 (MSB) PLL_SERIAL_1 00h R/W x SRL_MAN_IP PLL_SERIAL_2 01h R/W PLL_SERIAL_3 02h R/W x SERIALIZER 03h R/W BUFFER_OUT 04h R/W x PLL_SCG1 05h R/W x PLL_SCG2 ...
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... NXP Semiconductors 9.5.1 PLL serial registers Table 67. Legend default value Bit TDA9983B_1 Product data sheet PLL_SERIAL_1 register (address 00h) bit description Symbol Access Value x R/W 0* SRL_MAN_IP R SRL_REG_IP[2:0] R/W 000* 001 010 011 100 101 110 111 SRL_IZ[1:0] R/W 00* ...
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... NXP Semiconductors Table 68. Legend default value Bit Table 69. Legend default value Bit TDA9983B_1 Product data sheet PLL_SERIAL_2 register (address 01h) bit description Symbol Access Value SRL_PR[3:0] R/W 0000* 0001 0010 0011 0100 0101 0110 ...
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... NXP Semiconductors Table 70. Legend default value Bit Table 71. Legend default value Bit Table 72. Legend default value Bit Table 73. Legend default value Bit TDA9983B_1 Product data sheet SERIALIZER register (address 03h) bit description ...
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... NXP Semiconductors Table 73. Legend default value Bit Table 74. PLL_SCGNx registers (address 07h to 08h) bit description Legend default value Address Register Bit 08h PLL_SCGN2 SCG_NDIV[10:8] 07h PLL_SCGN1 SCG_NDIV[7:0] Table 75. PLL_SCGRx registers (address 09h to 0Ah) bit description Legend default value ...
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... NXP Semiconductors Table 76. Legend default value Bit Table 77. Legend default value Bit Table 78. Legend default value Bit TDA9983B_1 Product data sheet PLL_DE register (address 0Bh) bit description Symbol Access Value PLLDE_IZ[1:0] R/W 00 ...
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... NXP Semiconductors Table 79. Legend default value Bit Table 80. TESTx registers (address 0Fh and 10h) bit description Legend default value Address Register Bit Symbol 0Fh TEST1 TSTSERPHOE TST_NOSC 0 TST_HVP 10h TEST2 PWD1V8 0 DIVTESTOE ...
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... NXP Semiconductors Table 81. Legend default value Bit 9.5.2 Current page address register Table 82. Legend default value Bit 9.6 Information frames and packets page register definitions The current page address for the Information frames and packets page is 10h. The configuration of the registers for this page is given in ...
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Table 83. I C-bus registers of memory page 10h Register Sub R/W addr 7 (MSB) Not used 00h - : : : Not used 1Fh - VSP_IF_TYPE 20h R/W VSP_IF_VERSION 21h R/W VSP_IF_LENGTH 22h R/W x VSP_IF_CHECKSUM 23h R/W ...
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Table 83. I C-bus registers of memory page 10h Register Sub R/W addr 7 (MSB) VSP_IF_BYTE26 3Dh R/W VSP_IF_BYTE27 3Eh R/W Not used 3Fh - AVI_IF_TYPE 40h R/W AVI_IF_VERSION 41h R/W AVI_IF_LENGTH 42h R/W x AVI_IF_CHECKSUM 43h R/W AVI_IF_BYTE1 ...
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Table 83. I C-bus registers of memory page 10h Register Sub R/W addr 7 (MSB) AVI_IF_BYTE26 5Dh R/W AVI_IF_BYTE27 5Eh R/W Not used 5Fh - SPD_IF_TYPE 60h R/W SPD_IF_VERSION 61h R/W SPD_IF_LENGTH 62h R/W x SPD_IF_CHECKSUM 63h R/W SPD_IF_BYTE1 ...
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Table 83. I C-bus registers of memory page 10h Register Sub R/W addr 7 (MSB) SPD_IF_BYTE26 7Dh R/W SPD_IF_BYTE27 7Eh R/W Not used 7Fh - AUD_IF_TYPE 80h R/W AUD_IF_VERSION 81h R/W AUD_IF_LENGTH 82h R/W x AUD_IF_CHECKSUM 83h R/W AUD_IF_BYTE1 ...
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Table 83. I C-bus registers of memory page 10h Register Sub R/W addr 7 (MSB) AUD_IF_BYTE25 9Ch R/W AUD_IF_BYTE26 9Dh R/W AUD_IF_BYTE27 9Eh R/W Not used 9Fh - MPS_IF_TYPE A0h R/W MPS_IF_VERSION A1h R/W MPS_IF_LENGTH A2h R/W x MPS_IF_CHECKSUM ...
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Table 83. I C-bus registers of memory page 10h Register Sub R/W addr 7 (MSB) MPS_IF_BYTE24 BBh R/W MPS_IF_BYTE25 BCh R/W MPS_IF_BYTE26 BDh R/W MPS_IF_BYTE27 BEh R/W Not used BFh - : : : Not used FEh - CURPAGE_ADR ...
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... NXP Semiconductors 9.6.1 Vendor-specific InfoFrame registers Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a specification for the correct definition of data bytes. Table 84. VSP_IF_xx registers (address 20h to 3Eh) bit description Legend default value Address Register 20h VSP_IF_TYPE 21h ...
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... NXP Semiconductors Table 84. VSP_IF_xx registers (address 20h to 3Eh) bit description Legend default value Address Register 37h VSP_IF_BYTE20 38h VSP_IF_BYTE21 39h VSP_IF_BYTE22 3Ah VSP_IF_BYTE23 3Bh VSP_IF_BYTE24 3Ch VSP_IF_BYTE25 3Dh VSP_IF_BYTE26 3Eh VSP_IF_BYTE27 9.6.2 Auxiliary video information InfoFrame registers Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a specifi ...
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... NXP Semiconductors Table 85. AVI_IF_xx registers (address 40h to 5Eh) bit description Legend default value Address Register Bit 44h AVI_IF_BYTE1 AVI_IF_Y[1: AVI_IF_B[1: AVI_IF_S[1:0] 45h AVI_IF_BYTE2 AVI_IF_C[1: AVI_IF_M[1: AVI_IF_R[3:0] TDA9983B_1 Product data sheet Symbol Access Value Description ...
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... NXP Semiconductors Table 85. AVI_IF_xx registers (address 40h to 5Eh) bit description Legend default value Address Register Bit 46h AVI_IF_BYTE3 reserved AVI_IF_SC[1:0] 47h AVI_IF_BYTE4 AVI_IF_VIC[6:0] 48h AVI_IF_BYTE5 reserved AVI_IF_PR[3:0] 49h AVI_IF_BYTE6 LINE_E_TP_BAR[7:0] 4Ah AVI_IF_BYTE7 LINE_E_TP_BAR[15:8] R/W ...
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... NXP Semiconductors 9.6.3 Source product description InfoFrame registers Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a specification for the correct definition of data bytes. Table 86. SPD_IF_xx registers (address 60h to 7Eh) bit description Legend default value Address Register 60h SPD_IF_TYPE ...
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... NXP Semiconductors Table 86. SPD_IF_xx registers (address 60h to 7Eh) bit description Legend default value Address Register 6Bh SPD_IF_BYTE8 6Ch SPD_IF_BYTE9 6Dh SPD_IF_BYTE10 6Eh SPD_IF_BYTE11 6Fh SPD_IF_BYTE12 70h SPD_IF_BYTE13 71h SPD_IF_BYTE14 72h SPD_IF_BYTE15 73h SPD_IF_BYTE16 74h SPD_IF_BYTE17 75h SPD_IF_BYTE18 76h SPD_IF_BYTE19 77h SPD_IF_BYTE20 ...
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... NXP Semiconductors Table 86. SPD_IF_xx registers (address 60h to 7Eh) bit description Legend default value Address Register 7Ch SPD_IF_BYTE25 7Dh SPD_IF_BYTE26 7Eh SPD_IF_BYTE27 9.6.4 Audio InfoFrame registers Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a specification for the correct definition of data bytes. ...
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... NXP Semiconductors Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description Legend default value Address Register 84h AUD_IF_BYTE1 85h AUD_IF_BYTE2 TDA9983B_1 Product data sheet Bit Symbol Access Value AUD_IF_CT[3:0] R/W 3 reserved R AUD_IF_CC[2:0] R reserved R AUD_IF_SF[2:0] R AUD_IF_SS[1:0] R/W Rev. 01 — 20 May 2008 ...
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... NXP Semiconductors Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description Legend default value Address Register 86h AUD_IF_BYTE3 87h AUD_IF_BYTE4 88h AUD_IF_BYTE5 89h AUD_IF_BYTE6 8Ah AUD_IF_BYTE7 8Bh AUD_IF_BYTE8 8Ch AUD_IF_BYTE9 8Dh AUD_IF_BYTE10 8Eh AUD_IF_BYTE11 8Fh AUD_IF_BYTE12 90h AUD_IF_BYTE13 91h AUD_IF_BYTE14 92h AUD_IF_BYTE15 ...
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... NXP Semiconductors Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description Legend default value Address Register 9Bh AUD_IF_BYTE24 9Ch AUD_IF_BYTE25 9Dh AUD_IF_BYTE26 9Eh AUD_IF_BYTE27 9.6.5 MPEG source InfoFrame registers Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a specification for the correct definition of data bytes. ...
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... NXP Semiconductors Table 88. MPS_IF_xx registers (address A0h to BEh) bit description Legend default value Address Register A8h MPS_IF_BYTE5 A9h MPS_IF_BYTE6 AAh MPS_IF_BYTE7 ABh MPS_IF_BYTE8 ACh MPS_IF_BYTE9 ADh MPS_IF_BYTE10 AEh MPS_IF_BYTE11 AFh MPS_IF_BYTE12 B0h MPS_IF_BYTE13 B1h MPS_IF_BYTE14 B2h MPS_IF_BYTE15 B3h MPS_IF_BYTE16 B4h MPS_IF_BYTE17 ...
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... NXP Semiconductors 9.6.6 Current page address register Table 89. Legend default value Bit 9.7 Audio settings and content info packets page register definitions The current page address for the audio settings and content info packets page is 11h. The configuration of the registers for this page is given in ...
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Table 90. I C-bus registers of memory page 11h Register Sub R/W addr 7 (MSB) AIP_CNTRL_0 00h R/W x CA_I2S 01h R/W x For test 02h R/W x For test 03h R/W x LATENCY_RD 04h R/W ACR_CTS_0 05h R/W ...
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Table 90. I C-bus registers of memory page 11h Register Sub R/W addr 7 (MSB) CH_STAT_B_2_AP3_R 1Fh R/W ISRC1_PACKET_TYPE 20h R/W ISRC1_CTRL 21h R/W ISRC_ CONT ISRC1_RSVD 22h R/W UPC_EAN_ISRC_0 23h R/W UPC_EAN_ISRC_1 24h R/W UPC_EAN_ISRC_2 25h R/W UPC_EAN_ISRC_3 ...
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Table 90. I C-bus registers of memory page 11h Register Sub R/W addr 7 (MSB) ISRC1_PB27 3Eh R/W Not used 3Fh - ISRC2_PACKET_TYPE 40h R/W ISRC2_RSVD1 41h R/W ISRC2_RSVD2 42h R/W UPC_EAN_ISRC_16 43h R/W UPC_EAN_ISRC_17 44h R/W UPC_EAN_ISRC_18 45h ...
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Table 90. I C-bus registers of memory page 11h Register Sub R/W addr 7 (MSB) ISRC2_PB27 5Eh R/W Not used 5Fh - ACP_PACKET_TYPE 60h R/W ACP_TYPE 61h R/W ACP_RSVD 62h R/W ACP_PB0 63h R/W ACP_PB1 64h R/W ACP_PB2 65h ...
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Table 90. I C-bus registers of memory page 11h Register Sub R/W addr 7 (MSB) ACP_PB27 7Eh R/W Not used 7Fh - : : : Not used FEh - CURPAGE_ADR FFh W [1] R: reading register W: writing register ...
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... NXP Semiconductors 9.7.1 Audio input processor control registers Table 91. Legend default value Bit Table 92. Legend default value Bit Table 93. Legend default value Bit Table 94. ACR_CTS_x registers (address 05h to 07h) bit description Legend default value ...
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... NXP Semiconductors Table 95. ACR_N_x registers (address 08h to 0Ah) bit description Legend default value Address Register 0Ah ACR_N_2 09h ACR_N_1 08h ACR_N_0 Table 96. Legend default value Bit Table 97. Legend default value Bit Table 98. Legend default value ...
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... NXP Semiconductors Table 98. Legend default value Bit Table 99. Legend default value Bit TDA9983B_1 Product data sheet ENC_CNTRL register (address 0Dh) bit description Symbol Access Value CTL_CODE[1:0] R DC_CTL[1:0] R/W 00 DIP_FLAGS register (address 0Eh) bit description ...
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... NXP Semiconductors Table 99. Legend default value Bit Table 100. DIP_IF_FLAGS register (address 0Fh) bit description Legend default value Bit TDA9983B_1 Product data sheet DIP_FLAGS register (address 0Eh) bit description Symbol Access Value ISRC1 R R ACR ...
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... NXP Semiconductors Table 101. CH_STAT_B_x channel status bytes and 4 registers (address 14h to 17h) bit description Legend default value Address Register 14h CH_STAT_B_0 15h CH_STAT_B_1 16h CH_STAT_B_3 17h CH_STAT_B_4 Table 102. CH_STAT_B_2_APx_n channel status byte 2 registers (address 18h to 1Fh) bit description ...
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... NXP Semiconductors Table 103. ISRC1 packet registers (address 20h to 3Eh) bit description Legend default value Address Register 22h ISRC1_RSVD 23h UPC_EAN_ISRC_0 24h UPC_EAN_ISRC_1 25h UPC_EAN_ISRC_2 26h UPC_EAN_ISRC_3 27h UPC_EAN_ISRC_4 28h UPC_EAN_ISRC_5 29h UPC_EAN_ISRC_6 2Ah UPC_EAN_ISRC_7 2Bh UPC_EAN_ISRC_8 2Ch UPC_EAN_ISRC_9 2Dh UPC_EAN_ISRC_10 UPC_EAN_ISRC_10[7:0] ...
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... NXP Semiconductors Table 104. ISRC2 packet registers (address 40h to 5Eh) bit description Legend default value Address Register 40h ISRC2_PACKET_ TYPE 41h ISRC2_RSVD1 42h ISRC2_RSVD2 43h UPC_EAN_ISRC_16 UPC_EAN_ISRC_16[7:0] 44h UPC_EAN_ISRC_17 UPC_EAN_ISRC_17[7:0] 45h UPC_EAN_ISRC_18 UPC_EAN_ISRC_18[7:0] 46h UPC_EAN_ISRC_19 UPC_EAN_ISRC_19[7:0] 47h ...
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... NXP Semiconductors Table 104. ISRC2 packet registers (address 40h to 5Eh) bit description Legend default value Address Register 5Ch ISRC2_PB25 5Dh ISRC2_PB26 5Eh ISRC2_PB27 9.7.3 Audio content protection packet registers Below is an example of use. Please refer to HDMI 1.2a specification for the correct definition of data bytes. ...
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... NXP Semiconductors Table 105. ACP packet registers (address 60h to 7Eh) bit description Legend default value Address Register Bit 64h ACP_PB1 ACP_PB_BYTE_1[7: ACP_PB_BYTE_1[5: ACP_PB_BYTE_1[2:1] 0 65h ACP_PB2 ACP_PB_BYTE_2[7:0] 66h ACP_PB3 ACP_PB_BYTE_3[7:0] 67h ACP_PB4 ACP_PB_BYTE_4[7:0] 68h ACP_PB5 ACP_PB_BYTE_5[7:0] ...
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... NXP Semiconductors Table 105. ACP packet registers (address 60h to 7Eh) bit description Legend default value Address Register Bit 69h ACP_PB6 ACP_PB_BYTE_6[7:0] 6Ah ACP_PB7 ACP_PB_BYTE_7[7:0] 6Bh ACP_PB8 ACP_PB_BYTE_8[7:0] 6Ch ACP_PB9 ACP_PB_BYTE_9[7:0] 6Dh ACP_PB10 ACP_PB_BYTE_10[7:0] 6Eh ACP_PB11 ACP_PB_BYTE_11[7:0] ...
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... NXP Semiconductors Table 105. ACP packet registers (address 60h to 7Eh) bit description Legend default value Address Register Bit 71h ACP_PB14 ACP_PB_BYTE_14[7:0] 72h ACP_PB15 ACP_PB_BYTE_15[7:0] 73h ACP_PB16 ACP_PB_BYTE_16[7:0] 74h ACP_PB17 ACP_PB_BYTE_17[7:0] 75h ACP_PB18 ACP_PB_BYTE_18[7:0] 76h ACP_PB19 ACP_PB_BYTE_19[7:0] ...
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... NXP Semiconductors Table 105. ACP packet registers (address 60h to 7Eh) bit description Legend default value Address Register Bit 7Ah ACP_PB23 ACP_PB_BYTE_23[7:0] 7Bh ACP_PB24 ACP_PB_BYTE_24[7:0] 7Ch ACP_PB25 ACP_PB_BYTE_25[7:0] 7Dh ACP_PB26 ACP_PB_BYTE_26[7:0] 7Eh ACP_PB27 ACP_PB_BYTE_27[7:0] 9.7.4 Current page address register Table 106 ...
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Table 107. I C-bus registers of memory page 12h Register Sub R/W addr 7 (MSB) Not used 00h - : : : Not used B7h - HDCP_TX33 B8h R/W x Not used B9h - : : : Not used ...
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... NXP Semiconductors 9.8.1 HDMI control registers Table 108. HDCP_TX33 register (address B8h) bit description Legend default value Bit 9.8.2 Current page address register Table 109. CURPAGE_ADR register (address FFh) bit description Legend default value Bit 10. Limiting values Table 110. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134) ...
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... NXP Semiconductors 12. Static characteristics Table 112. Supplies DDA(FRO_3V3) DDA(PLL_3V3 1. 1. DDC(1V8) PP Typical values are measured at V and unless otherwise specified. amb Symbol Parameter TDA9983BHW/8 and TDA9983BHW/15 V free running oscillator 3.3 V analog supply voltage DDA(FRO_3V3) V PLL 3.3 V analog supply voltage ...
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... NXP Semiconductors b) Output 1080p (RGB Table 113. LV-TTL digital inputs and outputs DDA(FRO_3V3) DDA(PLL_3V3 1. 1. DDC(1V8) PP Typical values are measured at V and unless otherwise specified. amb Symbol Parameter Not 5 V tolerant inputs: pins HSYNC, VSYNC, AP[7:0], ACLK, TM, A0, A1, VPA[7:0], VPB[7:0], VPC[7:0], VCLK, DE ...
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... NXP Semiconductors 13. Dynamic characteristics Table 115. Timing characteristics DDA(FRO_3V3) DDA(PLL_3V3 1. 1. DDC(1V8) PP Typical values are measured at V DDA(FRO_3V3) and unless otherwise specified. amb Symbol Parameter Supplies: pins DDC(1V8) DDD(3V3) t delay time d Clock inputs: pins VCLK, VPA[7:0], VPB[7:0], VPC[7:0]; see ...
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... NXP Semiconductors 13.1 Input format In Table 116 been mapped to Y (YUV space)/G (RGB space) and VPC has been mapped to C space)/R (RGB space). Table 116. Input format Input pins Signal RGB Video port A VPA[0] C [0]/B[0] B[0] B VPA[1] C [1]/B[1] B[1] B VPA[2] C [2]/B[2] B[2] B VPA[3] C [3]/B[3] ...
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... NXP Semiconductors 13.2 Example of supported video The TDA9983B supports all EIA/CEA-861B, ATSC video input formats. Table 117. Timing parameters for EIA/CEA-861B Format nr. Format V frequency (Hz) 59.94 Hz systems 1 (VGA) 640 480p 59.9401 2, 3 720 480p 59.9401 4 1280 720p 59.9401 5 1920 1080i 59.9401 6, 7 (NTSC) ...
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... NXP Semiconductors Table 117. Timing parameters for EIA/CEA-861B Format nr. Format V frequency (Hz) 23, 24 720 288p 50 25, 26 720 576i 50 27, 28 720 288p 50 27, 28 720 288p 50 27, 28 720 288p 50 29, 30 1440 576p 50 [1] 31 1920 1080p 50 Various systems 32 1920 1080p 23.976 32 1920 1080p 24 33 1920 ...
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... NXP Semiconductors Table 118. Timing parameters for PC standards below 150 MHz Standard Format V frequency (Hz) XGA 1024 786p 60.004 1024 786p 70.069 1024 786p 75.029 [1] 1024 786p 84.997 1024 786i 86.957 [1] 1152 864p 75.000 [1] 1152 864p 84.999 [1] 1280 960p 60 [1] 1280 960p 85 ...
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... NXP Semiconductors VCLK t clk(H) HSYNC/HREF CONTROL VSYNC/VREF INPUTS DE/FREF VPA[7: VPB[7: VPC[7: h(D) t su(D) Fig 16. Timing (rising edge) input B R VCLK HSYNC/HREF CONTROL VSYNC/VREF INPUTS DE/FREF VPB[7:0]; VPA[3: h(D) t su(D) Fig 17. Timing ITU656-like double edge (rising and falling) input ...
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... NXP Semiconductors VCLK t clk(H) HSYNC/HREF CONTROL VSYNC/VREF INPUTS DE/FREF VPB[7:0]; VPA[3:0] Y0 VPC[7:0]; VPA[7: Fig 19. Timing semi-planar external synchronization (rising edge) input B R TDA9983B_1 Product data sheet t t clk(L) h( su(D) Rev. 01 — 20 May 2008 TDA9983B ...
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... NXP Semiconductors 14. Application information LO Fig 20. Application diagram for Set-Top Box DVD READ ENGINE Fig 21. Application diagram for DVD player MICROPROCESSOR MASTER audio, S/PDIF and I MPEG2 DECODER MASTER HDMI SOURCE Fig 22. Transmitter connection with external world TDA9983B_1 Product data sheet G ADC DSP ...
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... NXP Semiconductors 15. Package outline HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body mm; exposed die pad y exposed die pad pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max 0.15 1.05 0.27 mm 1.2 0.25 0.05 0.95 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included ...
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... NXP Semiconductors 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Soldering: additional information The package of this device supports the reflow soldering process only. 18. Abbreviations Table 121 ...
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... NXP Semiconductors Table 121. Abbreviations Acronym DVB DVC DVD DVI D-VHS EAV EDID ROM E-EDID FIFO HBM HDCP HDD HDMI HDTV HPD ID IRQ ISRC KSV LO L-PCM LSB LUT LV-TTL MSB PAL PCM PLL PVR RGB Rx SAV STB S/PDIF TMDS Tx UPC/EAN YUV ...
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... NXP Semiconductors 19. Revision history Table 122. Revision history Document ID Release date TDA9983B_1 20080520 TDA9983B_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 20 May 2008 TDA9983B 150 MHz pixel rate HDMI transmitter Supersedes - © NXP B.V. 2008. All rights reserved. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 8 8.1 System clock 8.2 Video input processor . . . . . . . . . . . . . . . . . . . . 8 8.3 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 18 8.3.1 Timing extraction generator . . . . . . . . . . . . . . 18 8.3.2 Data enable generator . . . . . . . . . . . . . . . . . . 18 8 ...
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... NXP Semiconductors 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 116 20 Legal information 117 20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 117 20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 117 20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 117 21 Contact information 117 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 150 MHz pixel rate HDMI transmitter Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. ...