adv7171a-dbrd Analog Devices, Inc., adv7171a-dbrd Datasheet - Page 36

• Manufacturer Part Number: adv7171a-dbrd
• Description: Digital Pal/ntsc Video Encoder With 10-bit Ssaf ?nd Advanced Power Management
• Manufacturer: Analog Devices, Inc.

ADV7170/ADV7171
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3 TO 0 (PCE15 TO PCE0, PCO15
TO PCO0)/(TXE15 TO TXE0, TXO15 TO TXO0)
(Subaddress [SR4–SR0] = 12H to 15H)
These 8-bit-wide registers are used to enable the NTSC
pedestal/PAL teletext on a line-by-line basis in the vertical
blanking interval for both odd and even fields. Figure 48 and
Figure 49 show the four control registers. A Logic Level 1 in any
of the bits of these registers has the effect of turning the pedestal
off on the equivalent line when used in NTSC. A Logic Level 1
in any of the bits of these registers has the effect of turning on
teletext on the equivalent line when used in PAL.
FIELD 1/3
FIELD 1/3
FIELD 2/4
FIELD 2/4
FIELD 1/3
FIELD 1/3
FIELD 2/4
FIELD 2/4
TELETEXT REQUEST CONTROL REGISTER TC07
(TC07 TO TC00)
(Address [SR4 to SR0] = 19H)
Teletext control register is an 8-bit-wide register. See Figure 50.
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCO15
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCE15
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
PCO7
TXO15
TXE15
PCE7
TXO7
TXE7
PCO14 PCO13
PCE14
TXO14
PCO6
TXE14
PCE6
TXO6
TXE6
Figure 48. Pedestal Control Registers
Figure 49. Teletext Control Registers
PCE13
TXO13
PCO5
PCE5
TXE13
TXO5
TXE5
PCO12
PCE12
TXO12
PCO4
PCE4
TXE12
TXO4
TXE4
PCO11
PCO3
PCE11
TXO11
TXE11
PCE3
TXO3
TXE3
PCO10
PCE10
TXO10
PCO2
TXE10
PCE2
TXO2
TXE2
LINE 8
PCO9
PCO1
PCE1
PCE9
LINE 8 LINE 7
TXO1
TXO9
TXE1
TXE9
LINE 7
PCO8
PCO0
PCE0
PCE8
TXO0
TXO8
TXE0
TXE8
Rev. B | Page 36 of 64
TTXREQ Rising Edge Control (TC07 to TC04)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a maximum
of 15 CLOCK cycles. See Figure 59.
TTXREQ Falling Edge Control (TC03 to TC00)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of
15 CLOCK cycles. This controls the active window for teletext
data. Increasing this value reduces the amount of teletext bits
below the default of 360. If Bit TC03 to Bit TC00 are 00Hex
when bits TC07 to TC04 are changed, the falling edge of
TTXREQ tracks that of the rising edge (that is, the time
between the falling and rising edge remains constant).
See Figure 59.
CGMS_WSS REGISTER 0 C/W0 (C/W07 TO C/W00)
(Address [SR4 to SR0] = 16H)
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51
shows the operations under the control of this register.
C/W0 BIT DESCRIPTION
CGMS Data Bits (C/W03 to C/W00)
These four data bits are the final four bits of the CGMS data
output stream. Note it is CGMS data ONLY in these bit
positions; that is, WSS data does not share this location.
CGMS CRC Check Control (C/W04)
When this bit is enabled (1), the last six bits of the CGMS data
(that is, the CRC check sequence) are calculated internally by
the ADV7170/ADV7171. If this bit is disabled (0), the CRC
values in the register are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
When this bit is set (1), CGMS is enabled for odd fields. Note
this is valid only in NTSC mode.
CGMS Even Field Control (C/W06)
When this bit is set (1), CGMS is enabled for even fields. Note
this is valid only in NTSC mode.
WSS Control (C/W07)
When this bit is set (1), wide screen signaling is enabled. Note
this is valid only in PAL mode.