ad420-32-reel Analog Devices, Inc., ad420-32-reel Datasheet - Page 4

• Manufacturer Part Number: ad420-32-reel
• Description: Serial Input 16-bit 4 Ma-20 Ma, 0 Ma-20 Ma Dac
• Manufacturer: Analog Devices, Inc.

AD420
THREE-WIRE INTERFACE
Parameter
Data Clock Period
Data Clock Low Time
Data Clock High Time
Data Stable Width
Data Setup Time
Data Hold Time
Latch Delay Time
Latch Low Time
Latch High Time
Serial Output Delay Time
Clear Pulsewidth
Three-Wire Interface Fast Edges on Digital Input
With a fast rising edge (<10 ns) on one of the serial inputs
(CLOCK, DATA IN, LATCH) while another input is logic
high, the part may be triggered into a test mode and the con-
tents of the data register may become corrupted, which may
result in the output being loaded with an incorrect value. If fast
edges are expected on the digital input lines, it is recommended
that the latch line remain at Logic 0 during serial loading of the
DAC. Similarly, the clock line should remain low during updates
of the DAC via the latch pin. Alternatively, the addition of
small value capacitors on the digital lines will slow down the
edge.
Timing Requirements
DATA OUT
DATA OUT
DATA IN
DATA IN
CLOCK
CLOCK
Table II. Timing Specification for Three-Wire Interface
LATCH
LATCH
Figure 2. Timing Diagram for Three-Wire Interface
1 0 1 1
t
t
CL
DS
0 0
t
DW
WORD "N – 1"
t
WORD "N"
CK
1
t
DH
0 0
t
Label
t
t
t
t
t
t
t
t
t
t
t
CH
CK
CL
CH
DW
DS
DH
LD
LL
LH
SD
CLR
t
(T
LD
1 1 1
A
t
= –40 C to +85 C, V
LL
t
SD
0 0
Limit
300
80
80
125
40
5
80
80
80
225
50
1 1
t
LH
1 0
WORD "N + 1"
1
WORD "N"
0 0 1
CC
1 1
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
= +12 V to +32 V)
–4–
Parameter
Asynchronous Clock Period
Asynchronous Clock Low Time
Asynchronous Clock High Time
Data Stable Width (Critical Clock Edge) t
Data Setup Time (Critical Clock Edge) t
Data Hold Time (Critical Clock Edge)
Clear Pulsewidth
ASYNCHRONOUS INTERFACE
Note in the timing diagram for asynchronous mode operation
each data word is “framed” by a START (0) bit and a STOP
(1) bit. The data timing is with respect to the rising edge of the
CLOCK at the center of each bit cell. Bit cells are 16 clocks
long, and the first cell (the START bit) begins at the first clock
following the leading (falling) edge of the START bit. Thus the
MSB (D15) is sampled 24 clock cycles after the beginning of
the START bit, D14 is sampled at clock number 40, and so on.
During any “dead time” before writing the next word the
DATA IN pin must remain at Logic 1.
The DAC output updates when the STOP bit is received. In
the case of a “framing error” (the STOP bit sampled as a 0) the
AD420 will output a pulse at the DATA OUT pin one clock
period wide during the clock period subsequent to sampling the
STOP bit. The DAC output will not update if a “framing error”
is detected.
Table III. Timing Specifications for Asynchronous Interface
DATA IN
DATA IN
DATA IN
Figure 3. Timing Diagram for Asynchronous Interface
CLOCK
CLOCK
CLOCK
(INTERNALLY GENERATED LATCH)
CLOCK COUNTER STARTS HERE
EXPANDED TIME VIEW BELOW
0 1
0
2
START BIT
CONFIRM START BIT
8
1
t
t
ADS
ACL
EXPANDED TIME VIEW BELOW
t
t
ADW
ACK
0
16
t
ACH
t
ADH
DATA BIT 15
Label Limit Units
t
t
t
t
t
SAMPLE BIT 15
24
ACK
ACL
ACH
ADW
ADS
ADH
CLR
0
400
50
150
300
50
20
50
1
BIT 14
REV. F
ns min
ns min
ns min
ns min
ns min
ns min
ns min