dac1405d650 NXP Semiconductors, dac1405d650 Datasheet
dac1405d650
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dac1405d650 Summary of contents
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... In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. The DAC1405D650 also includes and 8 clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current. ...
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... Product data sheet Dual 14-bit DAC 650 Msps and 8 interpolating Description plastic thermal enhanced thin quad flat package; 100 leads; body mm; exposed die pad Rev. 01 — 4 May 2009 DAC1405D650 Version SOT638-1 © NXP B.V. 2009. All rights reserved ...
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... Block diagram DAC1405D650 FIR1 14 LATCH I0 to I13 I 2 dual port/ interleaved data modes FIR1 LATCH Q13 CLKP CLOCK GENERATOR/ PLL CLKN RESET_N Fig 1. Block diagram SDO SCS_N SDIO SCLK SPI NCO Cos Sin mixer + FIR2 FIR3 2 2 mixer FIR2 ...
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... I11 20 I10 Fig 2. Pin configuration DAC1405D650_1 Product data sheet Dual 14-bit DAC 650 Msps and 8 interpolating DAC1405D650HW AGND Rev. 01 — 4 May 2009 DAC1405D650 75 V DDA(3V3) 74 AUXBP 73 AUXBN 72 AGND 71 V DDA(1V8 DDA(1V8) 69 GAPOUT 68 VIRES 67 d ...
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... digital ground data input bit data input bit 0 (LSB digital supply voltage 1 digital ground 38 - test mode 2 (to connect to DGND digital ground Rev. 01 — 4 May 2009 DAC1405D650 © NXP B.V. 2009. All rights reserved ...
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... DAC B output current 74 O complementary auxiliary DAC B output current 75 P analog supply voltage 3 analog ground 77 P analog supply voltage 1 analog ground 79 P analog supply voltage 1 analog ground Rev. 01 — 4 May 2009 DAC1405D650 © NXP B.V. 2009. All rights reserved ...
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... analog ground 95 P analog supply voltage 1 analog ground 97 P analog supply voltage 1 analog ground 99 P analog supply voltage 1.8 V 100 G analog ground [ analog ground Rev. 01 — 4 May 2009 DAC1405D650 © NXP B.V. 2009. All rights reserved ...
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... CLKP, CLKN, VIRES and GAPOUT referenced to AGND pins I13 to I0, Q13 to Q0, SDO, SDIO, SCLK, SCS_N and RESET_N referenced to GNDIO pins IOUTAP, IOUTAN, IOUTBP, IOUTBN, AUXAP, AUXAN, AUXBP and AUXBN referenced to AGND Conditions Rev. 01 — 4 May 2009 DAC1405D650 Min Max Unit 0.5 +4.6 V 0.5 +4 ...
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... MHz 640 Msps interpolation; NCO on; All MHz 640 Msps interpolation; NCO low power on Power-down mode full power-down; All V DD DAC A and DAC B Sleep mode; 8 interpolation; NCO on Rev. 01 — 4 May 2009 DAC1405D650 Test Min Typ Max [1] I 3.0 3.3 3.6 I 3.0 3.3 3.6 I 1.7 1.8 1 ...
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... Conditions [2] CLKP; or CLKN V < gpd V < gpd = default register compliance range guaranteed amb external voltage 1.25 V Rev. 01 — 4 May 2009 DAC1405D650 amb Test Min Typ Max [1] [3] C 825 - 1575 [3] C 100 - +100 0 GNDIO - 1 ...
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... MHz at 0 dBFS s o 2.51 MHz f 2.71 MHz; offset kHz 2.71 MHz f 3.51 MHz; offset kHz 3.51 MHz f 4 MHz; offset kHz 4 MHz f 40 MHz; offset MHz Rev. 01 — 4 May 2009 DAC1405D650 amb Test Min Typ Max [ 2 160 C 1 ...
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... MHz 614.4 Msps; f data s 1 carrier MHz 2 carriers MHz 4 carriers MHz f = 640 Msps; 8 interpolation noise shaper disable noise shaper enable Figure 8). – dBc Rev. 01 — 4 May 2009 DAC1405D650 Test Min Typ Max [ [5] ...
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... NXP Semiconductors 10. Application information 10.1 General description The DAC1405D650 is a dual 14-bit DAC operating 650 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary weighted sub-DAC. With an input data rate 160 MHz, and a maximum output sampling rate of 650 Msps, the DAC1405D650 allows more fl ...
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... Read or Write mode access description Description Write mode operation Read mode operation below N1 and N0 indicate the number of bytes transferred after the instruction Number of bytes to be transferred Table 9 “Register allocation Rev. 01 — 4 May 2009 DAC1405D650 Number of bytes 1 byte transferred ...
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... SPI timing diagram SPI timing characteristics Parameter SCLK frequency SCLK pulse width SCS_N set-up time SCS_N hold time SDIO set-up time SDIO hold time RESET_N pulse width Rev. 01 — 4 May 2009 DAC1405D650 t w(SCLK) Table 8. Min Typ Max - - ...
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Table 9. Register allocation map Address Register name R/W Bit definition b7 0 00h COMMon R/W 3W_SPI 1 01h TXCFG R/W NCO_ON 2 02h PLLCFG R/W PLL_PD 3 03h FREQNCO_LSB R/W 4 04h FREQNCO_LISB R/W 5 05h FREQNCO_UISB R/W 6 ...
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... Access Value Description NCO_ON R NCO_LP_SEL R INV_SIN_SEL R Rev. 01 — 4 May 2009 DAC1405D650 serial interface bus type 0 4 wire SPI 1 3 wire SPI serial interface reset 0 no reset 1 performs a reset on all registers except 0x00 data input latch 1 at CLK rising edge ...
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... Access Value Description R/W FREQNCO_LISB register (address 04h) bit description Symbol Access Value Description R/W Rev. 01 — 4 May 2009 DAC1405D650 …continued modulation dual DAC: no modulation positive upper single sideband up-conversion positive lower single sideband up-conversion negative upper single sideband up-conversion negative lower single sideband up-conversion ...
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... Symbol Access Value Description R/W DAC_A_Cfg_3 register (address 0Bh) bit description Symbol Access Value R/W Rev. 01 — 4 May 2009 DAC1405D650 - upper intermediate 8-bits for the NCO frequency setting - most significant 8-bits for the NCO frequency setting - lower 8-bits for the NCO phase setting - most signifi ...
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... Symbol Access Value AUX_A[9:2] R/W - DAC_A_Aux_LSB register (address 1Bh) bit description Symbol Access Value AUX_A_PD R/W AUX_A[1:0] R/W Rev. 01 — 4 May 2009 DAC1405D650 DAC B power off DAC B Sleep mode 0 disabled 1 enabled lower 6-bits for the DAC B offset - less significant 2-bits for the DAC B gain ...
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... Table 29. Default settings are shown highlighted. Bit 10.3 Input data The setting applied to MODE_SEL (register 00h[3]; see defines whether the DAC1405D650 operates in the Dual-port mode or in the Interleaved mode (see Table 30. Bit 3 setting 0 1 10.3.1 Dual-port mode The data input for Dual-port mode operation is shown in DAC has its own independent data input ...
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... Figure 7 “Interleaved mode timing (8x interpolation, latch on rising I13 SELIQ (synchronous alternative) SELIQ (asynchronous alternative 1) SELIQ (asynchronous alternative 2) CLK dig Latch I output Latch Q output Interleaved mode timing (8x interpolation, latch on rising edge) Rev. 01 — 4 May 2009 DAC1405D650 FIR 1 FIR 2 FIR FIR 1 FIR 2 FIR 001aaj586 ...
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... NXP Semiconductors 10.4 Input clock The DAC1405D650 can operate with a clock frequency of 160 MHz in the Dual-port mode and up to 320 MHz in the Interleaved mode. The input clock is LVDS (see can also be interfaced with CML (see Fig 8. Fig 9. DAC1405D650_1 Product data sheet Dual 14-bit DAC 650 Msps and 8 interpolating ...
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... NXP Semiconductors 10.5 Timing The DAC1405D650 can operate at an update rate (f data rate (f diagram”. (CLKP-CLKN) Fig 10. Input timing diagram The typical performances are measured duty cycle but any timing within the limits of the characteristics will not alter the performance. In Table 31 The setting applied to PLL_DIV[1:0] (register 02h[4:3] ...
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... NXP Semiconductors 10.6 FIR filters The DAC1405D650 integrates three selectable Finite Impulse Response (FIR) filters which allows the device to use interpolation rates. All three interpolation filters have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than 0.0005 dB. The coefficients of the interpolation filters are given in coeffi ...
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... Dual 14-bit DAC 650 Msps and 8 interpolating ---------------- - MHz when f NCO ---------------- - 5 2 Table 34 “Inversion filter Rev. 01 — 4 May 2009 DAC1405D650 = 640 Msps and the default phase coefficients”. (1) (2) © NXP B.V. 2009. All rights reserved ...
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... The output current depends on the digital input data: I IOUTP I IOUTN The setting applied to CODING (register 00h[2]; see defines whether the DAC1405D650 operates with a binary input or a two’s complement input. Table 35 “DAC transfer function” when I O(fs) Table 35. Data 0 ... 8192 ...
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... Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit I coarse adjustment O(fs) Binary 0000 0001 0010 0011 0100 0101 0110 0111 Rev. 01 — 4 May 2009 DAC1405D650 (1 %) connected to O(fs) DAC1405D650 REF. BANDGAP DAC CURRENT SOURCES ARRAY 001aaj816 Table 20 and register 0Bh; see description”) and to DAC_B_GAIN Table 36 “I I (mA) O(fs) 1.6 3.0 4 ...
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... The coding of the fine gain adjustment is two’s complement. 10.11 Digital offset adjustment When the DAC1405D650 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. ...
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... Analog output The DAC1405D650 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected via a load resistor R ...
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... NXP Semiconductors 10.13 Auxiliary DACs The DAC1405D650 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground AUX The output current depends on the auxiliary DAC data: ...
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... DC interface to an Analog Quadrature Modulator (AQM) When the system operation requires to keep the DC component of the spectrum, the DAC1405D650 can use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC ...
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... AQM with a 3.3 V DAC1405D650 3.3 V 54.9 54.9 IOUTP IOUTN 1.27 k 1.27 k IOUTP/IOUTN V = 2.75 V o(cm 1.97 V o(dif)(p-p) provides an example interface with the auxiliary DACs to an AQM with a common mode input level. Rev. 01 — 4 May 2009 DAC1405D650 AQM (V i(cm) 442 BBP 442 BBN 768 768 BBP/BBN V = 1.7 V i(cm 1.26 V i(dif)(p-p) AQM i(cm) i(cm) ...
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... DAC1405D650 3.3 V 54.9 54.9 IOUTP IOUTN 634 k 634 k AUXP AUXN 442 k 442 k IOUTP/IOUTN V = 2.75 V o(cm 1.96 V o(dif)(p-p) Rev. 01 — 4 May 2009 DAC1405D650 AQM (V i(cm) 442 BBP 442 BBN 698 698 51.1 51.1 BBP/BBN V = 1.7 V i(cm 1.23 V i(dif)(p-p) offset correction AQM when using auxiliary DACs i(cm) ...
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... NXP Semiconductors 10.14.3 AC interface to an Analog Quadrature Modulator (AQM) When the AQM common mode voltage is close to ground, the DAC1405D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 18 input level when using auxiliary DACs. Fig 19. An example interface to a 0.5 V ...
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... Rev. 01 — 4 May 2009 DAC1405D650 © NXP B.V. 2009. All rights reserved ...
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... Product data sheet Dual 14-bit DAC 650 Msps and 8 interpolating Alternative parts Description dual 10-bit DAC dual 12-bit DAC Rev. 01 — 4 May 2009 DAC1405D650 Sampling frequency up to 650 Msps up to 650 Msps © NXP B.V. 2009. All rights reserved ...
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... scale (1) ( 0.20 14.1 7.1 14.1 7.1 0.5 0.09 13.9 6.1 13.9 6.1 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 4 May 2009 DAC1405D650 detail 16.15 16.15 0.75 1 0.2 0.08 0.08 15.85 15.85 0.45 EUROPEAN PROJECTION SOT638 (1) ( ...
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... Phase-Locked Loop Spurious-Free Dynamic Range Serial Peripheral Interface Time Division-Synchronous Code Division Multiple Access Upper Intermediate Significant Byte Wideband Code Division Multiple Access Worldwide Interoperability for Microwave Access Rev. 01 — 4 May 2009 DAC1405D650 © NXP B.V. 2009. All rights reserved ...
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... RMS value of the noise, including the harmonics given bandwidth centered around f DAC1405D650_1 Product data sheet Dual 14-bit DAC 650 Msps and 8 interpolating offset Rev. 01 — 4 May 2009 DAC1405D650 . © NXP B.V. 2009. All rights reserved ...
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... Revision history Document ID Release date DAC1405D650_1 20090504 DAC1405D650_1 Product data sheet Dual 14-bit DAC 650 Msps and 8 interpolating Data sheet status Change notice Product data sheet - Rev. 01 — 4 May 2009 DAC1405D650 Supersedes - © NXP B.V. 2009. All rights reserved ...
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... Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 4 May 2009 DAC1405D650 © NXP B.V. 2009. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com DAC1405D650 All rights reserved. Date of release: 4 May 2009 Document identifier: DAC1405D650_1 ...