epm3064a Altera Corporation, epm3064a Datasheet - Page 34

• Manufacturer Part Number: epm3064a
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet
34
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t
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Symbol
SU
H
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
PD1
PD2
SU
H
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
Table 21. EPM3128A Internal Timing Parameters (Part 2 of 2)
Table 22. EPM3256A External Timing Parameters
Symbol
Register setup time
Register hold time
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low–power adder
Input to non–registered
output
I/O input to non–registered
output
Global clock setup time
Global clock hold time
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay C1 = 35 pF
Array clock high time
Array clock low time
Minimum pulse width for
clear and preset
Parameter
Parameter
(2)
(5)
C1 = 35 pF
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(2)
(3)
Conditions
Conditions
(2)
(2)
(2)
Note (1)
Min
1.4
0.6
Min
5.2
0.0
1.0
3.0
3.0
2.7
0.3
1.0
3.0
3.0
3.0
–5
Max
0.8
0.5
1.2
0.7
1.1
1.4
1.4
1.4
4.0
–7
Note (1)
Speed Grade
Max
Speed Grade
7.5
7.5
4.8
7.3
Min
2.1
1.0
–7
Max
1.2
0.9
1.7
1.0
1.6
2.0
2.0
2.0
4.0
Min
6.9
0.0
1.0
4.0
4.0
3.6
0.5
1.0
4.0
4.0
4.0
Min
2.9
1.3
–10
Altera Corporation
–10
Max
6.4
9.7
10
10
Max
1.6
1.3
2.2
1.3
2.0
2.7
2.7
2.6
5.0
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns