adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 13

• Manufacturer Part Number: adsp-21367kbpz-2a
• Description: Sharc Processors
• Manufacturer: Analog Devices, Inc.

Table 5. Pin List
Name
SDCKE
SDA10
SDCLK0
SDCLK1
MS
FLAG[0]/IRQ0
FLAG[1]/IRQ1
FLAG[2]/IRQ2/
MS
FLAG[3]/TIMEXP/
MS
TDI
TDO
TMS
TCK
TRST
EMU
CLK_CFG
BOOT_CFG
0–1
2
3
1–0
1–0
Type
O/T (pu)
O/T (pu)
O/T
O/T
O/T (pu)
I/O
I/O
I/O with pro-
grammable pu
(for MS mode)
I/O with pro-
grammable pu
(for MS mode)
I (pu)
O/T
I (pu)
I
I (pu)
O/T (pu)
I
I
1
1
1
State During/
After Reset
(ID = 00x)
Pulled high/
driven high
Pulled high/
driven low
High-Z/driving
Pulled high/
driven high
High-Z/high-Z
High-Z/high-Z
High-Z/high-Z
High-Z/high-Z
Rev. A | Page 13 of 56 | August 2006
Description
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-
SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
SDRAM Clock Output 0.
SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple
SDRAM devices, handles the increased clock load requirements, eliminating need of
off-chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated.
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-
sponding banks of external memory. The MS
that change at the same time as the other address lines. When no external memory
access is occurring, the MS
tional memory access instruction is executed, whether or not the condition is true.
The MS
more information.
FLAG0/Interrupt Request 0.
FLAG1/Interrupt Request 1.
FLAG2/Interrupt Request 2/Memory Select 2.
FLAG3/Timer Expired/Memory Select 3.
Test Data Input (JTAG). Provides serial data for the boundary scan logic.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Mode Select (JTAG). Used to control the test state machine.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up, or held low for proper operation of the processor
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor.
Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/ADSP-21369
Analog Devices DSP Tools product line of JTAG emulator target board connectors only.
Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See
a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
Boot Configuration Select. These pins select the boot mode for the processor. The
BOOT_CFG pins must be valid before reset is asserted. See
the boot modes.
1
pin can be used in EPORT/FLASH boot mode. See the hardware reference for
ADSP-21367/ADSP-21368/ADSP-21369
3-0
lines are inactive; they are active, however, when a condi-
3-0
lines are decoded memory address lines
Table 7
for a description of
Table 8
for