adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 42

• Manufacturer Part Number: adsp-21367kbpz-2a
• Description: Sharc Processors
• Manufacturer: Analog Devices, Inc.

ADSP-21367/ADSP-21368/ADSP-21369
SPDIF Transmitter Input Data Timing
The timing requirements for the input port are given in
Table
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 38. SPDIF Transmitter Input Data Timing
1
Oversampling Clock (TxCLK) Switching Characteristics
The SPDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
Table 39. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Parameter
TxCLK Frequency for TxCLK = 768 × FS
TxCLK Frequency for TxCLK = 512 × FS
TxCLK Frequency for TxCLK = 384 × FS
TxCLK Frequency for TxCLK = 256 × FS
Frame Rate
DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SISFS
SIHFS
SISD
SIHD
SISCLKW
SISCLK
SITXCLKW
SITXCLK
1
1
1
1
38. Input signals (SCLK, FS, SDATA) are routed to the
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
Transmit Clock Width
Transmit Clock Period
SAMPLE EDGE
DAI_P20
DAI_P20
DAI_P20
DAI_P20
(TXCLK)
(SDATA)
(SCLK)
(FS)
-
-
-
-
1
1
1
1
Figure 32. SPDIF Transmitter Input Timing
t
SITXCLKW
Rev. A | Page 42 of 56 | August 2006
t
SISCLKW
t
SISFS
t
SISD
t
SITXCLK
Min
3
3
3
3
36
80
9
20
Min
t
t
SIHFS
SIHD
Max
147.5
98.4
73.8
49.2
192.0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
MHz
MHz
MHz
kHz