adsp-21371kswz-2a Analog Devices, Inc., adsp-21371kswz-2a Datasheet - Page 40

• Manufacturer Part Number: adsp-21371kswz-2a
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21371/ADSP-21375
S/PDIF Receiver
For the ADSP-21371, the following section describes timing as it
relates to the S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 38. S/PDIF Receiver Internal Digital PLL Mode Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
LRCLK Delay After SCLK
LRCLK Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit SCLK Width
(DATA CHANNEL A/B)
DAI_P20-1
Figure 28. S/PDIF Receiver Internal Digital PLL Mode Timing
DAI_P20-1
DAI_P20-1
(SCLK)
(FS)
DRIVE EDGE
Rev. B | Page 40 of 52 | June 2008
t
t
HOFSI
HDTI
t
DFSI
t
SCLKIW
t
DDTI
1.2 V, 266 MHz
Min
–2
–2
38.5
S/PDIF receiver information does not apply to the
ADSP-21375.
Max
5
5
SAMPLE EDGE
Unit
ns
ns
ns
ns
ns