adsp-2195mkca-160x Analog Devices, Inc., adsp-2195mkca-160x Datasheet - Page 2

• Manufacturer Part Number: adsp-2195mkca-160x
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-2195
ADSP-2195 DSP FEATURES
32K Words of On-Chip RAM, Configured as 16K Words
16K Words of On-Chip 24-bit ROM
Architecture Enhancements beyond ADSP-218x Family
Flexible Power Management with Selectable
Programmable PLL Supports 1
2.5 V Internal Operation Supports 3.3 V Compliant I/O
Three Full-Duplex Multichannel Serial Ports, Each
Two SPI-Compatible Ports with DMA Capability
One UART Port with DMA Capability
16 General-Purpose I/O Pins (Eight Dedicated/Eight
Three Programmable 32-Bit Interval Timers with
Up to 11 DMA Channels can be Active at any Given Time
Host Port With DMA Capability for Efficient, Glueless Host
2
On-Chip 24-bit RAM and 16K Words On-Chip
16-bit RAM
are Supported with Instruction Set Extensions for
Added Registers, Ports, and Peripherals
Power-Down and Idle Modes
Multiplication, Enabling Full-Speed Operation from
Low-Speed Input Clocks
Supporting H.100 Standard with A-Law and -Law
Companding in Hardware
Programmable from the External Memory Interface)
with Integrated Interrupt Support
Pulsewidth Counter, PWM Generation, and Externally
Clocked Timer Capabilities
Interface (16-Bit Transfers)
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
to 32
For current information contact Analog Devices at 800/262-5643
Frequency
External Memory Interface Features Include:
Boot Methods Include Booting Through External Memory
IEEE JTAG Standard 1149.1 Test Access Port Supports
144-Lead LQFP Package (20
Direct Access from the DSP to External Memory for
Support for DMA Block Transfers to/from
Separate Peripheral Memory Space with Parallel
Four General-Purpose Memory Select Signals that
Programmable Waitstate Logic with ACK Signal and
I/O Clock Rate Can Be Set to the Peripheral Clock Rate
Address Translation and Data Word Packing is Provided
Programmable Read and Write Strobe Polarity.
Separate Configuration Registers for the Four
Bus Request and Grant Signals Support the Use of the
Interface, SPI Ports, UART Port, or Host Interface
On-Chip Emulation and System Debugging
Mini-BGA Package (10
Data and Instructions.
External Memory.
Support for 224K External 16-Bit Registers.
Provide Access to Separate Banks of External
Memory. Bank Boundaries and Size Are User-
Programmable.
Separate Read and Write Wait Counts. Wait Mode
Completion Supports All Combinations of ACK
and/or Wait Count.
Divided by 1, 2, 4, 16, or 32 to Allow Interface to Slow
Memory Devices.
to Support an 8- or 16-Bit External Data Bus.
General-Purpose, Peripheral, and Boot
Memory Spaces.
External Bus by an External Device.
10
20
September 2001
1.25 mm)
1.4 mm) and 144-Lead
REV. PrA