adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 29

• Manufacturer Part Number: adsp-21266skstz-2b
• Description: Sharc Embedded Processor
• Manufacturer: Analog Devices, Inc.

Memory Write—Parallel Port
Use the specifications in
Figure 20
memory-mapped peripherals) when the ADSP-2126x is access­
ing external memory space.
Table 27. 8-Bit Memory Write Cycle
1
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALEW
ALERW
ADAS
ADAH
WW
ADWL
ADWH
ALEHZ
DWS
DWH
DAWH
1
1
CCLK
(if a hold cycle is specified, else H = 0)
for asynchronous interfacing to memories (and
AD15-8
AD7-0
ALE
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted
Address/Data 15–0 Hold After ALE Deasserted
WR Pulse Width
Address/Data 15–8 to WR Low
Address/Data 15–8 Hold After WR High
ALE Deasserted to Address/Data 15–0 in High-Z
Address/Data 7–0 Setup Before WR High
Address/Data 7–0 Hold After WR High
Address/Data to WR High
WR
RD
Table
27,
Table
VALID ADDRESS
VALID ADDRESS
28,
t
ADAS
t
ALEW
Figure
19, and
Figure 19. 8-Bit Memory Write Cycle
Rev. E | Page 29 of 48 | July 2008
t
ADAH
t
ALEHZ
t
ALERW
CCLK
ADSP-21261/ADSP-21262/ADSP-21266
t
ADWL
VALID ADDRESS
t
DAW H
Min
2 × t
1 × t
2.5 × t
0.5 × t
D – 2
0.5 × t
0.5 × t
0.5 × t
D
0.5 × t
D
t
WW
CCLK
CCLK
VALID DATA
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
t
DWS
– 2
– 0.5
– 2.0
– 0.8
– 1.5
– 1 + H
– 0.8
– 1.5 + H
t
DWH
t
ADWH
Max
0.5 × t
CCLK
+ 2.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns