saa7118 NXP Semiconductors, saa7118 Datasheet - Page 9

• Manufacturer Part Number: saa7118
• Description: Multistandard Video Decoder With Adaptive Comb Filter And Component Video Input
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 4:
9397 750 15219
Product data sheet
Symbol
AI34
AI21
V
AI22
AI2D
AI23
V
V
AI24
AI11
V
AI12
AI1D
AI13
V
V
AI14
AGNDA
AOUT
V
V
DNC13
DNC14
DNC18
DNC15
EXMCLR
CE
V
LLC
V
LLC2
RES
V
V
CLKEXT
ADP8
ADP7
ADP6
ADP5
SSA2
DDA2
DDA2A
SSA1
DDA1
DDA1A
DDA0
SSA0
DDD1
SSD1
DDD2
SSD2
Pin description
Pin
QFP160
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
LBGA156
G1
G4
H3
G3
H1
H2
H4
J1
J3
J2
J4
K1
K3
K2
K4
L1
L3
L2
M1
M3
M2
N1
N2
P2
N3
P3
N4
M4
P4
L4
N5
P5
M5
L5
N6
P6
M6
L6
N7
…continued
Type
I
I
P
I
I
I
P
P
I
I
P
I
I
I
P
P
I
P
O
P
P
NC
I/pu
I/O
I/pd
I/pd
I/pu
P
O
P
O
O
P
P
I
O
O
O
O
[1]
Rev. 06 — 22 December 2005
Description
analog input 34
analog input 21
ground for analog inputs AI2x
analog input 22
differential input for ADC channel 2 (pins AI24 to AI21)
analog input 23
analog supply voltage for analog inputs AI2x (3.3 V)
analog supply voltage for analog inputs AI2x (3.3 V)
analog input 24
analog input 11
ground for analog inputs AI1x
analog input 12
differential input for ADC channel 1 (pins AI14 to AI11)
analog input 13
analog supply voltage for analog inputs AI1x (3.3 V)
analog supply voltage for analog inputs AI1x (3.3 V)
analog input 14
analog signal ground
analog test output (do not connect)
analog supply voltage (3.3 V) for internal clock generation circuit
ground for internal Clock Generation Circuit (CGC)
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
external mode clear (with internal pull-down)
Chip Enable (CE) or reset input (with internal pull-up)
digital supply voltage 1 (peripheral cells)
line-locked system clock output (27 MHz nominal)
digital ground 1 (peripheral cells)
line-locked
reset output (active LOW)
digital supply voltage 2 (core)
digital ground 2 (core; substrate connection)
external clock input intended for analog-to-digital conversion of VSB
signals (36 MHz)
MSB of direct analog-to-digital converted output data (VSB)
MSB
MSB
MSB
Multistandard video decoder with adaptive comb filter
1 of direct analog-to-digital converted output data (VSB)
2 of direct analog-to-digital converted output data (VSB)
3 of direct analog-to-digital converted output data (VSB)
1
2
clock output (13.5 MHz nominal)
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SAA7118
9 of 170