saa7110a NXP Semiconductors, saa7110a Datasheet

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saa7110a

Manufacturer Part Number
saa7110a
Description
One Chip Front-end 1 Ocf1
Manufacturer
NXP Semiconductors
Datasheet

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Product specification
File under Integrated Circuits, IC22
DATA SHEET
SAA7110; SAA7110A
One Chip Front-end 1 (OCF1)
INTEGRATED CIRCUITS
1995 Oct 18

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saa7110a Summary of contents

Page 1

... DATA SHEET SAA7110; SAA7110A One Chip Front-end 1 (OCF1) Product specification File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 1995 Oct 18 ...

Page 2

... I C-BUS START SET-UP 21.1 Remarks to Table 66 22 APPLICATION INFORMATION 23 START-UP, SOURCE SELECT AND STANDARD DETECTION FLOW EXAMPLE 1995 Oct 18 SAA7110; SAA7110A 23.1 CODE 0 STARTUP and STANDARD Procedure 23.2 MODE 0 Source Select Procedure 23.3 MODE 1 Source Select Procedure 23.4 MODE 2 Source Select Procedure 23.5 MODE 3 Source Select Procedure 23 ...

Page 3

... Video phone Video picture grabbing. 3 GENERAL DESCRIPTION The one chip front-end SAA7110; SAA7110A is a digital multistandard colour decoder (OCF1) on the basis of the DIG-TV2 system with two integrated Analog-to-Digital Converters (ADCs), a Clock Generation Circuit (CGC) and Brightness Contrast Saturation (BCS) control. ...

Page 4

... Oct 18 PACKAGE DESCRIPTION plastic leaded chip carrier; 68 leads plastic leaded chip carrier; 68 leads PC ISA - BUS ONE VIDEO CHIP MEMORY CONTROLLER OCF1 VMC clock YUV - BUS Fig.1 System diagram. 4 Product specification SAA7110; SAA7110A VERSION SOT188-2 SOT188-2 VIDEO FRAME MEMORY MGC821 ...

Page 5

... AP TEST CONTROL BLOCK 1 SP 67, 51, 43, 68, 52, 44, 35 BYPASS CHROMINANCE C/CVBS CIRCUIT LUMINANCE CIRCUIT Y/CVBS Y Y SYNCHRONIZATION SAA7110 CIRCUIT SAA7110A PLIN (HL HSY HCL ODD (VL) RTCO Fig.2 Block diagram C-BUS 5 SDA INTERFACE 6 ...

Page 6

... Using CREF all interfaces on the YUV-bus are able to generate a bus timing with identical phase. 1995 Oct 18 DESCRIPTION f for 50 Hz/625 lines per field systems and 1560 h 1 output 0.5 f (CGCE = 1, output; CGCE = 0, high 2 LLC2 LLC 6 Product specification SAA7110; SAA7110A f for h ...

Page 7

... C-bus register 05H mode or register 18H mode. 2 C-bus bit RTSE = 1). 2 C-bus bit RTSE = 0. 2 C-bus bit RTSE = 1). 7 Product specification SAA7110; SAA7110A 2 C-bus is reset (waiting for 2 C-bus bit PULIO: PULIO = 1, 2 C-bus bit PULIO: 2 C-bus 2 C-bus bit RTSE = 0. ...

Page 8

... C-bus control. These signals are part of the digital YUV-bus 2 C-bus bits MS24 and MS34 and MUYC to LOW. 2 C-bus bit VBLKA = 0. (Vertical Blank test output; select 2 C-bus bit VBLKA = 1). 8 Product specification SAA7110; SAA7110A 2 C-bus bit SQPB = 1. 2 C-bus bit SQPB = 1. 2 C-bus bit SQPB = 1. 2 C-bus register ...

Page 9

... AI31 18 V SSA2 AI22 DDA2 AI21 21 V SS( AOUT 24 V DDA0 V 25 SSA0 26 LFCO 1995 Oct 18 SAA7110 SAA7110A Fig.3 Pin configuration. 9 Product specification SAA7110; SAA7110A 60 UV2 59 UV3 58 UV4 57 UV5 56 UV6 55 UV7 ...

Page 10

... FUNCTIONAL DESCRIPTION 9.1 Analog input processing (see Fig.5) The SAA7110; SAA7110A offers six analog signal inputs, two analog main channels with clamping circuit, analog amplifier, anti-alias filter and video CMOS ADC. A third analog channel also with clamping circuit, analog amplifier and anti-alias filter can be added or switched to both main channels directly before the ADCs ...

Page 11

... The pre-filtered luminance signal is fed to the synchronization stage. It's bandwidth is reduced to 1 MHz in a low-pass filter. 1995 Oct 18 SAA7110; SAA7110A The synchronization pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations ...

Page 12

Acrobat reader. white to force landscape pages to be ... 20, 16 DDA2 to V DDA4 18, 14 SSA2 to ...

Page 13

Acrobat reader. white to force landscape pages to be ... INPUT CHROMINANCE QUADRATURE INTERFACE BANDPASS DEMODULATOR BYPS DISCRETE TIME CHRS HUEC LOOP FILTER 68, ...

Page 14

Acrobat reader. white to force landscape pages to be ... LUMINANCE CIRCUIT CHROMINANCE PREFILTER PREF 2 AP TEST CONTROL 1 SP BLOCK PREFILTER SYNC ...

Page 15

... HSY = horizontal sync pulse. HCL = horizontal clamp pulse. 1995 Oct 18 ANALOG IN ADC 1 0 VBLK CLAMP 0 HCL CLAA 0 1 SBOT 0 NO CLAMP GAIN Fig.8 Clamp and gain flow chart. 15 Product specification SAA7110; SAA7110A GAIN 1 0 HSY WIPE GAIN GAIN SLOW GAIN MGC827 ...

Page 16

... IVAL *IWIP *IGAI gain accumulator (20 bits) actual gain value 8-bit (AGV dB HSY AGV update gain value 8-bit Fig.9 Luminance AGC flow chart. 16 Product specification SAA7110; SAA7110A decoder input 0 HSY 1 0 WIPE X 1 WVAL / 0 *IWIP FGV ...

Page 17

... DDA DDD note 2 CONDITIONS 4. 0.5 couple clamping current off 200 f < 5 MHz amplifier + AAF = bypass amplifier + AAF = bypass 11 17 Product specification SAA7110; SAA7110A MIN. MAX. 0.5 +7.0 V 0.5 +7.0 V 0.5 +7.0 V 0.5 +7.0 V 100 mV 65 +150 +80 2.5 W 2000 ...

Page 18

... HD;OTHER inputs 1995 Oct 18 CONDITIONS MIN. 0.5 3.0 0.5 2.4 3.0 0.5 2.0 I/Os at high impedance note 1 1.4 note 2 0 note 2 2.4 0.5 2 0 2 note Product specification SAA7110; SAA7110A TYP. MAX. UNIT + 2.6 V 0.6 ...

Page 19

... LLC2 and LLC 0.6 to 2.6 V 2 pF; note 6 LLC/LLC2 field 60 Hz field 50 Hz field 60 Hz field PAL NTSC 19 Product specification SAA7110; SAA7110A MIN. TYP. MAX 7 31 ...

Page 20

... MIN. 3rd harmonic pF: data outputs (plus HREF and VS); 1 (TTL load); L TYPICAL ANALOG DELAY AI21 TO ADCIN (AOUT) (ns Product specification SAA7110; SAA7110A TYP. MAX. UNIT 26.8 MHz ...

Page 21

... CLOCK OUTPUT LLC2 1995 Oct LLCH HD;DAT t SU;DAT t OHD PDZ t OHD LLCL LLCH OHD t dLLC2 Fig.10 Clock/data timing. 21 Product specification SAA7110; SAA7110A 2.4 V 1 2 HD;DAT 2 HD;DAT 2.4 V 0.6 V 2.6 V 1 OHD 2.4 V 0 ...

Page 22

... HRMV = 1 and HRFS = 0. 1995 Oct 2/LLC burst 191 127 processing delay CVBS 18 2/LLC 176 768 2/LLC 30 2/LLC 94 2/LLC 64 2/LLC 117 0 18 2/LLC 140 640 2/LLC 64 2/LLC 97 0 Fig.11 Horizontal timing. 22 Product specification SAA7110; SAA7110A 64 128 (1) YUV 2/LLC 4/LLC 118 2/LLC 97 MGC830 ...

Page 23

... Hz) UVn V634 1995 Oct ONE BUS CYCLE 764 765 766 U764 V764 U766 636 637 638 U636 V636 U638 Fig.12 HREF timing. 23 Product specification SAA7110; SAA7110A END OF ACTIVE LINE 767 V766 639 V638 MGC831 ...

Page 24

... Fig.13 Vertical timing. 24 Product specification SAA7110; SAA7110A 533 2/LLC 2/LLC 319 320 321 61 2/LLC 2/LLC 441 2/LLC 2/LLC 269 270 271 ...

Page 25

... HPLL-INCR. FSCPLL-INCR Fig.15 Real time control output timing. 25 Product specification SAA7110; SAA7110A t PD MGC833 SEQUENCE RESERVED (50 Hz SYSTEMS (60 Hz SYSTEMS ...

Page 26

... LLC2 LLC4 LLC4 26 Product specification SAA7110; SAA7110A PIXEL BYTE SEQUENCE FORMAT ...

Page 27

... Fig.16 YUV output signal range. XTALO 65 SAA7110 SAA7110A XTALI /-20 with external clock. Fig.17 Oscillator application. 27 Product specification SAA7110; SAA7110A 255 red 100% 240 red 75% 212 128 V-COMPONENT cyan 75% 44 cyan 100 MGC835 c. Y output range (R Y). ...

Page 28

... Table 4 System clock frequencies CLOCK XTAL LLC LLC2 LLC4 LLC8 ZERO PHASE LOOP CROSS DETECTION FILTER DETECTION DIVIDER Fig.18 Clock generation circuit. 28 Product specification SAA7110; SAA7110A FREQUENCY (MHz 26.8 26.8 29.5 24.545454 14.75 12.272727 7.375 6.136136 3.6875 3.068181 OSCILLATOR LLC DIVIDER LLC2 ...

Page 29

... CLOCK CLOCK I/O OUTPUT CONTROL ACTIVE CONTROL Fig.19 Power-on control circuit. PIN OUTPUT STATUS 29 Product specification SAA7110; SAA7110A RESET MGC838 FUNCTION direct switching to high impedance (outputs) or input mode (I/Os) for 20 to 200 ms 2 starting I C-bus reset sequence SA0DH = 7DH (VTRC = 0, RTSE = 1, HRMV = 1, SSTB = 0, SECS = 1) ...

Page 30

... order to read (the circuit is slave transmitter) 9CH for write, 9DH for read ( 9EH for write, 9FH for read ( 00H to 19H decoder part 1AH to 1FH reserved 20H to 34H front-end part 30 Product specification SAA7110; SAA7110A ACK DATA (n bytes) ACK P ...

Page 31

... XXX XXX XXX 143 142 141 CHCV7 CHCV6 CHCV5 CHCV4 151 150 149 SATN7 SATN6 SATN5 SATN4 31 Product specification SAA7110; SAA7110A (2) DATA BYTE 004 003 002 001 IDEL4 IDEL3 IDEL2 IDEL1 012 011 010 009 HSYB3 HSYB2 ...

Page 32

... IGAI1 IGAI0 GAI45 103 102 101 CLS4 XXX CLS3 111 110 109 IVAL7 IVAL6 IVAL5 32 Product specification SAA7110; SAA7110A (2) DATA BYTE 156 155 154 153 CONT3 CONT2 CONT1 164 163 162 161 HS6B3 HS6B2 HS6B1 ...

Page 33

... Subaddresses to be reset 7DH, 0E and 31 to 00H after RESET = 0 (CGCE = 0) or power-on (CGCE = 1). 2. All reserved XXX-bits must be set to LOW, XX-bit is don’t care. 3. AFCCS bit does not exist in SAA7110A due to advanced anti-alias filter characteristic, don’t care (XX). Table 8 OCF1 ...

Page 34

... Oct 18 DESCRIPTION 007 to 000) CONTROL BITS IDEL7 IDEL6 IDEL5 (2) 34 Product specification SAA7110; SAA7110A (1) IDEL4 IDEL3 IDEL2 IDEL1 IDEL0 ...

Page 35

... HCLB7 HCLB6 HCLB5 HCLB4 HCLB3 HCLB2 HCLB1 HCLB0 039 to 032) HCLS7 HCLS6 HCLS5 HCLS4 HCLS3 HCLS2 HCLS1 HCLS0 Product specification SAA7110; SAA7110A CONTROL BITS CONTROL BITS ...

Page 36

... Oct 18 047 to 040) HPHI7 HPHI6 HPHI5 Product specification SAA7110; SAA7110A CONTROL BITS HPHI4 HPHI3 HPHI2 HPHI1 ...

Page 37

... HUEC5 HUEC4 Product specification SAA7110; SAA7110A CONTROL BITS APER1 = 0; APER0 = 0 APER1 = 0; APER0 = 1 APER1 = 1; APER0 = 0 APER1 = 1; APER0 = 1 CORI1 = 0; CORI0 = 0 CORI1 = 0; CORI0 = 1 CORI1 = 1; CORI0 = 0 CORI1 = 1; CORI0 = 1 BPSS1 = 0; BPSS0 = 0 BPSS1 = 0; BPSS0 = 1 BPSS1 = 1; BPSS0 = 0 BPSS1 = 1; BPSS0 = 1 PREF = 0 PREF = 1 ...

Page 38

... CONTROL BITS SESE6 SESE5 SESE4 Product specification SAA7110; SAA7110A CONTROL BITS CKTQ3 CKTQ2 CKTQ1 CKTQ0 CONTROL BITS CKTS3 CKTS2 CKTS1 CKTS0 ...

Page 39

... HL switched to output pin 39 VL switched to output pin 40 TV/VCR mode select (VTRC); data bit D7 TV mode VTR mode 1995 Oct 18 103 to 096) 111 to 104) 39 Product specification SAA7110; SAA7110A CONTROL BITS LFIS1 = 0; LFIS0 = 0 LFIS1 = 0; LFIS0 = 1 LFIS1 = 1; LFIS0 = 0 LFIS1 = 1; LFIS0 = 1 COLO = 0 COLO = 1 CONTROL BITS ...

Page 40

... Automatic field detection(AUFD); data bit D7 Field state directly controlled via FSEL Automatic field detection 1995 Oct 18 119 to 112) 127 to 120) YDEL2 = 0; YDEL1 = 0; YDEL0 = 0 YDEL2 = 0; YDEL1 = 1; YDEL0 = 1 40 Product specification SAA7110; SAA7110A CONTROL BITS GPSW = 0 GPSW = 1 CHRS = 0 CHRS = 1 OEYC = 0 OEYC = 1 OEHV = 0 OEHV = 1 ...

Page 41

... SATN6 SATN5 SATN4 Product specification SAA7110; SAA7110A CONTROL BITS VNOI1 = 0; VNOI0 = 0 VNOI1 = 0; VNOI0 = 1 VNOI1 = 1; VNOI0 = 0 VNOI1 = 1; VNOI0 = 1 HRFS = 0 HRFS = 1 CHCV3 CHCV2 CHCV1 CHCV0 SATN3 ...

Page 42

... CONTROL BITS HS6S7 HS6S6 HS6S5 HS6S4 183 to 176) CONTROL BITS HC6B7 HC6B6 HC6B5 HC6B4 Product specification SAA7110; SAA7110A HS6B3 HS6B2 ...

Page 43

... BRIG7 BRIG6 BRIG5 Product specification SAA7110; SAA7110A CONTROL BITS CONTROL BITS HP6I4 HP6I3 HP6I2 HP6I1 ...

Page 44

... Analog input disable 3 (AIND3); data bit D6 Analog inputs 3 enabled Analog inputs 3 disabled Analog input disable 4 (AIND4); data bit D7 Analog inputs 4 enabled Analog inputs 4 disabled 1995 Oct 18 007 to 000) 44 Product specification SAA7110; SAA7110A CONTROL BITS AINS2 = 0 AINS2 = 1 AINS3 = 0 AINS3 = 1 AINS4 = 0 AIND4 = 1 FUSE1 = 0; FUSE0 = 0 FUSE1 = 0; FUSE0 = 1 FUSE1 = 1 ...

Page 45

... MUXC select channel 34 (MS34); data bit D6 Analog MUX3 controlled by MX34 Analog MUX3 controlled by MUXC Vertical blanking control off (VBCO); data bit D7 Vertical blanking on Vertical blanking off 1995 Oct 18 015 to 008) 45 Product specification SAA7110; SAA7110A CONTROL BITS REFS2 = 0 REFS2 = 1 REFS3 = 0 REFS3 = 1 REFS4 = 0 REFS4 = 1 MS24 = 0 MS24 = 1 MX241 = 0 ...

Page 46

... CLL214 Product specification SAA7110; SAA7110A CONTROL BITS MX341 = 0; MX340 = 0 MX341 = 0; MX340 = 1 MX341 = 1; MX340 = 0 MX341 = 1; MX340 = 1 CLTS = 0 CLTS = 1 MUYC = 0 MUYC = 1 YSEL = 0 YSEL = 1 CSEL = 0 CSEL = 1 GACO1 = 0; GACO0 = 0 GACO1 = 0; GACO0 = 1 GACO1 = 1; GACO0 = 0 GACO1 = 1; GACO0 = 1 CLL213 ...

Page 47

... CONTROL BITS CLL326 CLL325 CLL324 Product specification SAA7110; SAA7110A CLL223 CLL222 CLL221 CLL220 CLL313 CLL312 CLL311 CLL310 ...

Page 48

... CONTROL BITS WIPE7 WIPE6 WIPE5 WIPE4 079 to 072) CONTROL BITS SBOT7 SBOT6 SBOT5 SBOT4 Product specification SAA7110; SAA7110A #1 GAI22 GAI21 WIPE3 WIPE2 WIPE1 ...

Page 49

... GAIN CONTROL ANALOG GAIN GAI45 GAI44 2. Product specification SAA7110; SAA7110A #2 CONTROL BITS GAI33 GAI32 GAI31 CONTROL BITS IWIP1 = 0; IWIP0 = 0 IWIP1 = 0; IWIP0 = 1 IWIP1 = 1 ...

Page 50

... VBPS7 VBPS6 VBPS5 VBPS4 VBPS3 VBPS2 VBPS1 VBPS0 Product specification SAA7110; SAA7110A CONTROL BITS TWO2 = 0 TWO2 = 1 TWO3 = 0 TWO3 = 1 CLS2 = 0 CLS2 = 1 CLS3 = 0 CLS3 = 1 CLS4 = 0 CLS4 = 1 CONTROL BITS IVAL4 IVAL3 IVAL2 IVAL1 0 0 ...

Page 51

... GAD21 = 0; GAD20 = 0 GAD21 = 0; GAD20 = 1 GAD21 = 1; GAD20 = 0 GAD21 = 1; GAD20 = 1 GAD31 = 0; GAD30 = 0 GAD31 = 0; GAD30 = 1 GAD31 = 1; GAD30 = 0 GAD31 = 1; GAD30 = 1 51 Product specification SAA7110; SAA7110A CONTROL BITS CONTROL BITS GAS2 = 0 GAS2 = 1 GAS3 = 0 GAS3 = 1 ...

Page 52

... AOSL1 = 0; AOSL0 = 0 AOSL1 = 0; AOSL0 = 0 AOSL1 = 1; AOSL0 = 1 AOSL1 = 1; AOSL0 = 1 151 to 144) WVAL7 WVAL6 WVAL5 WVAL4 WVAL3 WVAL2 WVAL1 WVAL0 Product specification SAA7110; SAA7110A CONTROL BITS PULIO = 0 PULIO = 1 VBLKA = 0 VBLKA = 1 SQPB = 0 SQPB = 1 WRSE = 0 WRSE = 1 WRIS = 0 WRIS = 1 CONTROL BITS 0 0 ...

Page 53

... LLC cycle phase delay for CLAA path 1995 Oct 18 159 to 152) 167 to 160) UPDATE NEW GAIN - OLD GAIN GUDL5 GUDL4 GUDL3 GUDL2 GUDL1 GUDL0 >0 0 >7 0 always 1 53 Product specification SAA7110; SAA7110A CONTROL BITS CAD2 = 0 CAD2 = 1 CAD3 = 0 CAD3 = 1 CHSB = 0 CHSB = 1 OFTS = 0 OFTS = 1 CONTROL BITS ...

Page 54

... CVBS1 CVBS6 5 AD3 AD2 Fig.21 Mode 0; CVBS1. 54 Product specification SAA7110; SAA7110A CLS3 CLL32 CLAMP CON3 CLL31 MX340 ADC3 CHRS v BYPS MX341 CSEL MX240 YSEL ADC2 MX241 CLS2 CLL22 CLAMP CON2 CLL21 GAIN CON ...

Page 55

... AI21 AI22 1995 Oct 18 AD3 AD2 Fig.22 Mode 1; CVBS2. AD3 AD2 Fig.23 Mode 2; CVBS3. AD3 CHROMA LUMA AD2 Fig.24 Mode 3; CVBS4. AD3 AD2 Fig.25 Mode 4; CVBS5. 55 Product specification SAA7110; SAA7110A CHROMA LUMA MGC841 CHROMA LUMA MGC842 MGC843 CHROMA LUMA MGC844 ...

Page 56

... AI22 1995 Oct 18 AD3 AD2 Fig.26 Mode 5; CVBS6. AD3 AD2 Fig.27 Mode C1. AD3 AD2 Fig.28 Mode C2. AD3 AD2 Fig.29 Mode C3. 56 Product specification SAA7110; SAA7110A CHROMA LUMA MGC845 CHROMA LUMA MGC846 CHROMA LUMA MGC847 CHROMA LUMA MGC848 ...

Page 57

... BAH B8H 7CH 78H 05H 05H 03H 03H 57 Product specification SAA7110; SAA7110A ...

Page 58

... Hz. 1995 Oct 18 MODE 91H 91H D2H 03H 03H 83H 0XXXXXXX 60H 60H 60H Fig.30 Anti-alias filter graph for SAA7110A. 58 Product specification SAA7110; SAA7110A D2H 42H B1H C1H 83H A3H 13H 23H 1XXXXXXX 60H 44H 60H ...

Page 59

... CONTROL BITS CORI1 1995 Oct 18 (3) (2) ( Fig.31 Anti-alias filter graph for SAA7110. 64 handbook, halfpage 32 0 CORI0 Product specification SAA7110; SAA7110A MGC850 (MHz) MGC851 Fig.32 Coring function. ...

Page 60

... Fig.34 Luminance control: SU06H, 50 Hz/CVBS mode, prefilter on and coring off (40 to 43H). 1995 Oct 43H 42H 41H 40H Product specification SAA7110; SAA7110A MGC852 43H 53H 73H 63H 40H (MHz) MGC853 43H 42H 41H 40H 6 ...

Page 61

... VY (dB Fig.36 Luminance control: SU06H mode, prefilter off and coring off. 1995 Oct 83H 82H 81H 80H Product specification SAA7110; SAA7110A MGC854 03H 13H 33H 23H 00H (MHz) MGC855 (MHz) ...

Page 62

... Fig.38 Luminance control: SU06H, 60 Hz/CVBS mode, prefilter on and coring off. 1995 Oct 18 C3H C2H C1H C0H Product specification SAA7110; SAA7110A MGC856 (MHz) MGC857 43H 53H 73H 63H 40H (MHz) ...

Page 63

... Fig.40 Luminance control: SU06H, 60 Hz/CVBS mode, prefilter off and coring off. 1995 Oct Product specification SAA7110; SAA7110A MGC858 43H 42H 41H 40H (MHz) MGC859 03H 13H 33H 23H 00H (MHz) ...

Page 64

... Fig.41 Luminance control: SU06H mode, prefilter off and coring off. 18 handbook, full pagewidth VY (dB Fig.42 Luminance control: SU06H mode, prefilter on and coring off. 1995 Oct 18 83H 82H 81H 80H 4 C3H C2H C1H C0H Product specification SAA7110; SAA7110A MGC860 (MHz) MGC861 (MHz) ...

Page 65

... Hz horizontal sync (HSY) stop 60 Hz horizontal clamp (HCL) begin horizontal clamp (HCL) stop 60 Hz horizontal sync after PHI1 60 Hz luminance brightness 65 Product specification SAA7110; SAA7110A BINARY HEX ...

Page 66

... SET vertical blanking pulse RESET ADCs gain control mixer control #3 integration value white peak mixer control #4 gain update level 66 Product specification SAA7110; SAA7110A BINARY HEX start ...

Page 67

... SSA Fig.43 Application diagram. 67 Product specification SAA7110; SAA7110A V DD1 C15 100 nF V DD2 C14 100 nF C13 V DD3 100 nF V DD4 C12 100 nF V DD5 C11 V SS 100 ...

Page 68

... SSA V DDA V DDD The OCF1 supports for special applications the use of an external CGC (SAA7197). For normal operation the built-in CGC fulfils all requirements. Fig.44 Application diagram with external Clock Generator Circuit (CGC). SAA7110 SAA7110A ...

Page 69

... SECAM? yes yes no B&W50? yes no B&W60? yes NTSC? no NTSC set-up B&W60 set-up stop Fig.45 Software flow example. 69 Product specification SAA7110; SAA7110A mode 0 set-up precharge clamping capacitor mode XX0XXX00 XX1XXX00 NTSC? yes XX1XXXXX XX0XXX01 no PAL set-up yes SECAM? SECAM set-up MGC864 ...

Page 70

... SUB 11 WRITE 59 !CHCV SUB 2E WRITE 9A !VBPS PAUSE %150 !150ms IF 1 @XX0XXX01 THEN GOTO SECAM ELSE PRINT "PAL" GOTO STOP 1995 Oct 18 SAA7110; SAA7110A #SECAM SUB 0D WRITE 07 !SECS -> 1 PRINT "SECAM" GOTO STOP #STOP 23.2 MODE 0 Source Select Procedure SLAVE 9C !OCF1 SUB 06 WRITE 00 ...

Page 71

... SUB 06 WRITE 80 !Y+C MODE 8 SUB 20 WRITE 3C !AI41=Y, AI32=C SUB 21 WRITE 27 !REFS ON SUB 22 WRITE C1 !AD2->LUMA, AD3->CHR 1995 Oct 18 SAA7110; SAA7110A SUB 2C WRITE 23 !CLAMP SELECT SUB 30 WRITE 44 !Gain AD2 active SUB 31 WRITE 75 !AOSL -> 01 SUB 21 WRITE 21 !REFS OFF CLAMP AKTIV 71 Product specification ...

Page 72

... 24.33 24.33 23.62 23.62 25.27 25.27 1.27 24.13 24.13 22.61 22.61 25.02 25.02 0.958 0.958 0.930 0.930 0.995 0.995 0.05 0.950 0.950 0.890 0.890 0.985 0.985 REFERENCES JEDEC EIAJ MO-047AC 72 Product specification SAA7110; SAA7110A detail max. max. max. 1.22 1.44 0.51 0.18 0.18 ...

Page 73

... C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes 1995 Oct 18 SAA7110; SAA7110A 25.3 Wave soldering Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used ...

Page 74

... Philips. This specification can be ordered using the code 9398 393 40011. 1995 Oct components conveys a license under the Philips’ system provided the system conforms to the I 74 Product specification SAA7110; SAA7110A 2 C patent to use the 2 C specification defined by ...

Page 75

... Philips Semiconductors One Chip Front-end 1 (OCF1) 1995 Oct 18 SAA7110; SAA7110A NOTES 75 Product specification ...

Page 76

Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, ...

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