saa7113h-v2 NXP Semiconductors, saa7113h-v2 Datasheet - Page 20

• Manufacturer Part Number: saa7113h-v2
• Description: 9-bit Video Input Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14232
Product data sheet
Fig 19. Luminance and sync processing
I
2
C-BUS
PREFILTER
PREFILTER
INTERFACE
SCL
I
2
SYNC
LUM
C-BUS
24
CONTROL
SDA
PREF
SYNCHRONIZATION CIRCUIT
23
8.5 Synchronization
CHROMINANCE
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is
further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the
phase detectors where they are compared with the sub-divided clock frequency. The
resulting output signal is applied to the loop filter to accumulate all phase deviations.
Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to generate the line frequency
control signal LFCO (see
The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is
also done within the synchronization circuit.
The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh.
BYPS
TRAP
VBLB
HTC[1:0]
LUMINANCE CIRCUIT
VNOI0
VNOI1
MACROVISION
PROCESSOR
SYNC SLICER
DETECTOR
VERTICAL
RTS0
26
FIDT
BAND-PASS
VARIABLE
HSB[7:0]
HSS[7:0]
FILTER
BPSS0
BPSS1
AUFD
PREF
FSEL
COPRO
COUNTER
DETECTOR
RTS1
PHASE
FINE
27
HLCK
Rev. 02 — 9 May 2005
Figure
MATCHING
AMPLIFIER
VBLB
HTC[1:0]
19).
HPLL
LOOP FILTER
DETECTOR
COARSE
PHASE
2
WEIGHTING
HTC[1:0]
ADDING
STAGE
AND
Y
APER0
APER1
VBLB
OSCILLATOR 2
INCS
DISCRETE
DAC6
TIME
CLOCK CIRCUIT
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
9-bit video input processor
LINE-LOCKED
GENERATION
GENERATOR
GENERATOR
CRYSTAL
CIRCUIT
CLOCKS
SAA7113H
CLOCK
CLOCK
CLOCK
mhb329
17
10
11
40
32
31
20 of 75
LLC
V
V
CE
XTALI
XTAL
SSA0
DDA0