ep2sgx60e Altera Corporation, ep2sgx60e Datasheet - Page 37

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ep2sgx60e

Manufacturer Part Number
ep2sgx60e
Description
4. Serial Configuration Devices Epcs1, Epcs4, Epcs16, Epcs64, And Epcs128 Data Sheet
Manufacturer
Altera Corporation
Datasheet

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Figure 4–19. AS Configuration Timing
Altera Corporation
May 2008
CONF_DONE
f
Symbol
CLK
INIT_DONE
Table 4–25. Timing Parameters for AS Configuration (Part 1 of 2)
nCONFIG
nSTATUS
User I/O
DATA0
ASDO
nCSO
DCLK
DCLK
DCLK
DCLK
DCLK
DCLK
Tri-stated with internal pull-up resistor
Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
frequency from Cyclone FPGA
frequency from Stratix II or Cyclone II FPGA (40 MHz)
frequency from Stratix II or Cyclone II FPGA (20 MHz)
frequency from Cyclone III FPGA
frequency from Stratix III FPGA
t CF2ST1
Read Address
Figure 4–19
scheme using a serial configuration device.
Table 4–25
t
t
ODIS
nCLK2D
Table 4–24. Read Operation Parameters (Part 2 of 2)
Symbol
t SU
Parameter
t H
bit N
shows the timing parameters for AS configuration mode.
shows the timing waveform for FPGA AS configuration
bit N − 1
Output disable time after read
Clock falling edge to data
(1)
(1)
Parameter
bit 1
t CH
t CL
bit 0
(1)
Configuration Handbook, Volume 2
Min
14
20
10
20
15
Min
136 Cycles
Typ
17
26
13
30
25
Max
15
15
Max
20
40
20
40
40
User Mode
MHz
MHz
MHz
MHz
MHz
Unit
Unit
4–37
ns
ns

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