mm908e621 Freescale Semiconductor, Inc, mm908e621 Datasheet - Page 30

• Manufacturer Part Number: mm908e621
• Description: Integrated Quad Half-bridge And Triple High-side With Embedded Mcu And Lin For High End Mirror
• Manufacturer: Freescale Semiconductor, Inc

indicate the source of a wake-up from Sleep mode: Either LIN
bus activity or an event on the L0 wake-up input terminal.
POR— Power On Reset bit
writing a logic “1” to this location.
PINR— Reset forced from external Reset terminal bit
external reset RST_A terminal. Bit is cleared by writing an
logic “1” to this location.
WDR— Watch Dog Reset bit
wrong watchdog timer reset. Clear WDR by writing a logic “1”
to WDR.
LIN PHYSICAL LAYER
wire communication in automotive applications. The LIN
physical layer is designed to meet the LIN physical layer
specification.
limitation and thermal shutdown. An internal pullup resistor
with a serial diode structure is integrated, so no external
pullup components are required for the application in a slave
node. The fall time from dominant to recessive and the rise
time from recessive to dominant is controlled. The symmetry
between both slew rate controls is guaranteed.
30
908E621
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Read
Write
POR
In addition the register includes two flags which will
This read/write bit is set after power on. Bit is cleared by
This read/write bit is set after an reset was forced on the
This read/write flag is set due to watchdog time-out or
The LIN bus terminal provides a physical layer for single-
The LIN driver is a low-side MOSFET with internal current
1 = Reset due to power on
0 = no power on reset
1 = reset source is external reset terminal
0 = no external reset
POR
Bit7
1
Register Name and Address: RSR - $0D
PINR
6
0
WDR
5
0
HTR
4
0
LVR
3
0
2
0
0
ANALOG DIE INPUTS/OUTPUTS
LINWF LOWF
1
0
Bit0
0
HTR— High Temperature Reset bit
certain value. Bit is cleared by writing a logic “1” to this
location.
LVR— Low Voltage Reset bit
coming from the main voltage regulator falls below a certain
value. Bit is cleared by writing a logic “1” to this location.
LINWF— LIN Wake-Up Flag
wake-up. Bit is cleared by writing a logic “1” to this location.
L0WF— L0 Wake-Up Flag
caused an wake-up. Bit is cleared by writing a logic “1” to this
location.
10 and 20kBit/s as well as high baud rates for test and
programming. The slew rate can be adapted with 2 bits
SRS[1:0] in the System Control Register. The initial slew rate
is optimized for 20kBit/s.
from external disturbance, guaranteeing communication
during external disturbance.
PSON bit in the System Control Register (SYSCTL).
LINCL bit in the System Status Register (SYSSTAT) is set
and the LIN transceiver is disabled after a certain time.
This read/write bit is set if the chip temperature exceeds a
This read/write bit is set if the external VDD voltage
This read/write bit is set if a bus activity was the case of an
This read/write bit is set if a event on the L0 terminal
The slew rate can be selected for optimized operation at
The LIN terminal offers high susceptibility immunity level
The LIN transmitter circuitry is enabled by setting the
If the transmitter works in the current limitation region, the
1 = reset source is watchdog
0 = no watchdog reset
1 = reset due to high temperature condition
0 = no high temperature reset
1 = reset due to low voltage condition
0 = no low voltage reset
1 = Wake-up due to bus activity
0 = no wake-up due to bus activity
1 = Wake-Up due to L0 terminal
0 = no Wake-Up due to L0 terminal
Analog Integrated Circuit Device Data
Freescale Semiconductor