mm908e622 Freescale Semiconductor, Inc, mm908e622 Datasheet - Page 23

• Manufacturer Part Number: mm908e622
• Description: Mm908e622 Integrated Quad Half-bridge, Triple High-side And Ec Glass Driver With Embedded Mcu And Lin For High End Mirror
• Manufacturer: Freescale Semiconductor, Inc

RESET TERMINAL (
It is an open drain with pullup resistor and must be connected
to the
INTERRUPT TERMINAL (
indicating errors or wake-up events. It is an open drain with
pullup resistor and must be connected to the
the MCU.
ADC SUPPLY/REFERENCE TERMINALS (VDDA/
VREFH AND VSSA/VREFL)
analog-to-digital converter (ADC).
the ADC.
capacitor be placed between these terminals.
MCU POWER SUPPLY TERMINALS (EVDD AND
EVSS)
terminals. The MCU operates from a single power supply.
duration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU.
Analog Integrated Circuit Device Data
Freescale Semiconductor
RST_A
IRQ_A
VDDA and VSSA are the power supply terminals for the
VREFH and VREFL are the reference voltage terminals for
The supply and reference signals are internally connected.
It is recommended that a high quality ceramic decoupling
For details refer to the 68HC908EY16 datasheet.
EVDD and EVSS are the power supply and ground
Fast signal transitions on MCU terminals place high, short-
RST
is the interrupt output terminal of the analog die
is the bidirectional reset terminal of the analog die.
terminal of the MCU.
RST_A
IRQ_A
)
)
IRQ
terminal of
TEST MODE TERMINAL (TESTMODE)
terminal has to be forced to GND.
VDD to bring the analog die into Test mode. In Test mode the
Reset Time-out (80ms) is disabled and the LIN receiver is
disabled
PSON bit needs to be set within 80ms. If not the device will
automatically enter sleep mode.
MCU TEST TERMINAL (FLSVPP)
be either left open (not connected) or can be connected to
GND.
EXPOSED PAD TERMINAL
package conducts heat from the chip to the PCB board. For
thermal performance the pad must be soldered to the PCB
board. It is recommended that the pad be connected to the
ground potential.
For details refer to the 68HC908EY16 datasheet.
This terminal is for test purpose only. In the application this
For Programming/Test this terminal has to be forced to
NOTE: After detecting a RESET (internal or external) the
This terminal is for test purposes only. This terminal should
The exposed pad terminal on the bottom side of the
VDDA/VREFH
VSSA/VREFL
µC
EVDD
EVSS
0,1µF
Functional Terminal Description
4,7µF
Functional Description
VDD
VSS
Analog
Die
908E622
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