ksz8851-mql Micrel Semiconductor, ksz8851-mql Datasheet - Page 24

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ksz8851-mql

Manufacturer Part Number
ksz8851-mql
Description
Single-port Ethernet Mac Controller With 8/16-bit Or 32-bit Non-pci Interface
Manufacturer
Micrel Semiconductor
Datasheet
Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
Detection of Linkup
Link status wake events are useful to indicate a linkup in the network’s connectivity status.
Wake-up Packet
Wake-up packets are certain types of packets with specific CRC values that a system recognizes as a ‘wake up’ frame.
The KSZ8851M supports up to four users defined wake-up frames as below:
1. Wake-up frame 0 is defined in wakeup frame registers (0x30 – 0x3B) and is enabled by bit 0 in wakeup frame control
register (0x2A).
2. Wake-up frame 1 is defined in wakeup frame registers (0x40 – 0x4B) and is enabled by bit 1 in wakeup frame control
register (0x2A).
3. Wake-up frame 2 is defined in wakeup frame registers (0x50 – 0x5B) and is enabled by bit 2 in wakeup frame control
register (0x2A).
4. Wake-up frame 3 is defined in wakeup frame registers (0x60 – 0x6B) and is enabled by bit 3 in wakeup frame control
register (0x2A).
Magic Packet™
Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished by
sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable of
receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller, and when the LAN
controller receives a Magic Packet frame, it will alert the system to wake up.
Magic Packet is a standard feature integrated into the KSZ8851M. The controller implements multiple advanced power-
down modes including Magic Packet to conserve power and operate more efficiently.
Once the KSZ8851M has been put into Magic Packet Enable mode (WFCR[7]=1), it scans all incoming frames addressed
to the node for a specific data sequence, which indicates to the controller this is a Magic Packet (MP) frame.
A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address
(SA), Destination Address (DA), which may be the receiving station’s IEEE address or a multicast or broadcast address
and CRC.
The specific sequence consists of 16 duplications of the IEEE address of this node, with no breaks or interruptions. This
sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The
synchronization stream allows the scanning state machine to be much simpler. The synchronization stream is defined as
6 bytes of FFh. The device will also accept a broadcast frame, as long as the 16 duplications of the IEEE address match
the address of the machine to be awakened.
Example:
If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be
scanning for the data sequence (assuming an Ethernet frame):
DESTINATION SOURCE – MISC - FF FF FF FF FF FF - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -
11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -
11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -
11 22 33 44 55 66 - MISC - CRC.
There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or an
IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node at the
frame’s destination.
If the LAN controller scans a frame and does not find the specific sequence shown above, it discards the frame and takes
no further action. If the KSZ8851M controller detects the data sequence, however, it then alerts the PC’s power
management circuitry (assert the PME pin) to wake up the system.
Physical Layer Transceiver (PHY)
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
February 2009
24
M9999-021309-1.1

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